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<title>lume/na/arch/riscv/trap/trap_vector.S, branch master</title>
<subtitle>A general-purpose operating system with Linux ABI compatibility
</subtitle>
<id>https://git.richardqin.org/lume/atom?h=master</id>
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<updated>2026-07-10T03:31:46Z</updated>
<entry>
<title>refactor: promote new architecture to repository root</title>
<updated>2026-07-10T03:31:46Z</updated>
<author>
<name>Richard Qin</name>
<email>richard.qin.x@gmail.com</email>
</author>
<published>2026-07-10T03:31:46Z</published>
<link rel='alternate' type='text/html' href='https://git.richardqin.org/lume/commit/?id=e90b72ec3082588b296956730bd2930cf8d5d671'/>
<id>urn:sha1:e90b72ec3082588b296956730bd2930cf8d5d671</id>
<content type='text'>
Archive the deprecated implementation under lume-legacy, make the new kernel the default root-level build, and update repository entry points without changing kernel behavior.
</content>
</entry>
<entry>
<title>feat: establish bootable new architecture checkpoint</title>
<updated>2026-07-10T03:24:56Z</updated>
<author>
<name>Richard Qin</name>
<email>richard.qin.x@gmail.com</email>
</author>
<published>2026-07-10T03:24:56Z</published>
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<id>urn:sha1:1767d390fbf3d0c65389de46caf0b6d43ef3b6ad</id>
<content type='text'>
Replace the compressed boot path with a relocatable higher-half RISC-V entry, expand memory and SMP support, and add the driver, TTY, VFS, exec, signal, syscall, initramfs, and self-test infrastructure needed for a bootable kernel checkpoint.
</content>
</entry>
<entry>
<title>feat: add kernelvec for S-mode trap handling and improve trap_vector functionality</title>
<updated>2026-05-13T08:21:37Z</updated>
<author>
<name>Richard Qin</name>
<email>richard.qin.x@gmail.com</email>
</author>
<published>2026-05-13T08:21:37Z</published>
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<id>urn:sha1:6831a609f505ce26db4c5dddad5039c9c3e6747a</id>
<content type='text'>
</content>
</entry>
<entry>
<title>feat: add initial RISC-V architecture support and core kernel functionality</title>
<updated>2026-04-16T17:05:31Z</updated>
<author>
<name>Richard Qin</name>
<email>richard.qin.x@gmail.com</email>
</author>
<published>2026-04-16T17:05:31Z</published>
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<id>urn:sha1:e2564d112ba03b432f9f44f445cbc4a3ed85751a</id>
<content type='text'>
- Implement MMU hardware primitives for RISC-V SV39 in mmu.h
- Create trap vector control primitives in trap.h
- Define trap frame structure for RISC-V in trapframe.h
- Add assembly routines for context switching in swtch.S
- Implement trap vector entry/exit in trap_vector.S
- Introduce basic error number definitions in errno.h
- Provide placement new/delete operators in new.h
- Define kernel panic handler in panic.h and implement in panic.cc
- Establish basic type definitions in types.h
- Create the kernel main entry point in main.cc with global initialization
- Add synchronization primitives using spinlocks in spinlock.h and spinlock.cc
- Define per-CPU state tracking for interrupts in cpu_state.h
- Create a linker script for the kernel in linker.ld
- Update module makefiles for kernel and library components
</content>
</entry>
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