lume/na/arch/riscv/trap, branch master

refactor: promote new architecture to repository root

2026-07-10T03:31:46Z

Archive the deprecated implementation under lume-legacy, make the new kernel the default root-level build, and update repository entry points without changing kernel behavior.

feat: establish bootable new architecture checkpoint

2026-07-10T03:24:56Z

Replace the compressed boot path with a relocatable higher-half RISC-V entry, expand memory and SMP support, and add the driver, TTY, VFS, exec, signal, syscall, initramfs, and self-test infrastructure needed for a bootable kernel checkpoint.

feat: add ret_from_fork trampoline for newly forked processes

2026-05-13T08:22:01Z

feat: add kernelvec for S-mode trap handling and improve trap_vector functionality

2026-05-13T08:21:37Z

feat: add exception table implementation with binary search and initialization

2026-05-13T08:04:53Z

feat: add RISC-V specific trap handling logic and dispatch functions

2026-05-13T08:03:17Z

feat: add RISC-V configuration and memory management enhancements

2026-05-02T15:31:46Z

Co-authored-by: Copilot

feat: add initial RISC-V architecture support and core kernel functionality

2026-04-16T17:05:31Z

- Implement MMU hardware primitives for RISC-V SV39 in mmu.h - Create trap vector control primitives in trap.h - Define trap frame structure for RISC-V in trapframe.h - Add assembly routines for context switching in swtch.S - Implement trap vector entry/exit in trap_vector.S - Introduce basic error number definitions in errno.h - Provide placement new/delete operators in new.h - Define kernel panic handler in panic.h and implement in panic.cc - Establish basic type definitions in types.h - Create the kernel main entry point in main.cc with global initialization - Add synchronization primitives using spinlocks in spinlock.h and spinlock.cc - Define per-CPU state tracking for interrupts in cpu_state.h - Create a linker script for the kernel in linker.ld - Update module makefiles for kernel and library components