lume/na/arch/riscv, branch masterA general-purpose operating system with Linux ABI compatibility
https://git.richardqin.org/lume/atom?h=master2026-07-10T03:31:46Zrefactor: promote new architecture to repository root2026-07-10T03:31:46ZRichard Qinrichard.qin.x@gmail.com2026-07-10T03:31:46Zurn:sha1:e90b72ec3082588b296956730bd2930cf8d5d671
Archive the deprecated implementation under lume-legacy, make the new kernel the default root-level build, and update repository entry points without changing kernel behavior.
feat: establish bootable new architecture checkpoint2026-07-10T03:24:56ZRichard Qinrichard.qin.x@gmail.com2026-07-10T03:24:56Zurn:sha1:1767d390fbf3d0c65389de46caf0b6d43ef3b6ad
Replace the compressed boot path with a relocatable higher-half RISC-V entry, expand memory and SMP support, and add the driver, TTY, VFS, exec, signal, syscall, initramfs, and self-test infrastructure needed for a bootable kernel checkpoint.
feat: update module.mk files to include additional source files for various subsystems2026-05-13T08:32:52ZRichard Qinrichard.qin.x@gmail.com2026-05-13T08:32:52Zurn:sha1:63dc025705f6533b91fb1a7d26e6ed864efd9900feat: implement user-kernel memory copy functions with validation2026-05-13T08:28:06ZRichard Qinrichard.qin.x@gmail.com2026-05-13T08:28:06Zurn:sha1:8cbf571e56fd5ef631b51f4e5e3f181df1a529fffeat: add syscall dispatch implementation for RISC-V architecture2026-05-13T08:25:58ZRichard Qinrichard.qin.x@gmail.com2026-05-13T08:25:58Zurn:sha1:b321b8b0180daa74cdd3c1285267702932af7b41feat: add ret_from_fork trampoline for newly forked processes2026-05-13T08:22:01ZRichard Qinrichard.qin.x@gmail.com2026-05-13T08:22:01Zurn:sha1:e7314f76d9edfbee2f676fad90ae6a727403263ffeat: add kernelvec for S-mode trap handling and improve trap_vector functionality2026-05-13T08:21:37ZRichard Qinrichard.qin.x@gmail.com2026-05-13T08:21:37Zurn:sha1:6831a609f505ce26db4c5dddad5039c9c3e6747afeat: add exception table implementation with binary search and initialization2026-05-13T08:04:53ZRichard Qinrichard.qin.x@gmail.com2026-05-13T08:04:53Zurn:sha1:73773984eee26ea92b2777b40a9dc608e1b010aafeat: add RISC-V specific trap handling logic and dispatch functions2026-05-13T08:03:17ZRichard Qinrichard.qin.x@gmail.com2026-05-13T08:03:17Zurn:sha1:8b12351ec2e08b62f807195f5eb18abce3cbd276feat: add support for Copy-On-Write in SV39 page table management2026-05-13T07:49:50ZRichard Qinrichard.qin.x@gmail.com2026-05-13T07:49:50Zurn:sha1:11053d1cab4fcaac7bf8808bd51647875cee1bf3