lume/src/drivers/uart.cc, branch masterA general-purpose operating system with Linux ABI compatibility
https://git.richardqin.org/lume/atom?h=master2026-07-10T03:31:46Zrefactor: promote new architecture to repository root2026-07-10T03:31:46ZRichard Qinrichard.qin.x@gmail.com2026-07-10T03:31:46Zurn:sha1:e90b72ec3082588b296956730bd2930cf8d5d671
Archive the deprecated implementation under lume-legacy, make the new kernel the default root-level build, and update repository entry points without changing kernel behavior.
feat: implement FDT-based memory discovery and add comprehensive debug logging to exec syscalls2026-04-14T14:47:15ZRichard Qinrichard.qin.x@gmail.com2026-04-14T14:47:15Zurn:sha1:ac9741e12222e72bad3414bc6f588e70a3d130ccImportant: License changed from MIT to GPL.2026-01-04T17:31:55ZRichard Qinrichard.qin.x@gmail.com2026-01-04T17:31:55Zurn:sha1:51a788fa9e13ead0c504a1369797f8b49d73634c
Rewrote the README based on the actual project.
feat(file-system): implement read and write FAT32 File System and basic shell2026-01-04T06:05:49ZRichard Qinrichard.qin.x@gmail.com2026-01-04T06:05:49Zurn:sha1:d3cf3f08d1343d6b265516d5a79ce2d197b59d26dev(sell): add simple libc and implement shell2026-01-02T02:09:37ZRichard Qinrichard.qin.x@gmail.com2026-01-02T02:09:37Zurn:sha1:1c8e37f63d413a559825020289178d442537449e
please see the log for detail.
dev(device): implement VirtIO2026-01-01T07:04:47ZRichard Qinrichard.qin.x@gmail.com2026-01-01T07:04:47Zurn:sha1:2dde56422dcfb94affee2baffc8d240ad16ad4b2
See dev log for detail
dev:Refactor Memory Management and Process Management2025-12-31T10:00:55ZRichard Qinrichard.qin.x@gmail.com2025-12-31T10:00:55Zurn:sha1:dbba25aa24f86c1f8c3a0589c82985840adc1b6bfeat: add preemptive scheduling, SBI timer support and FDT parser.2025-12-13T15:21:03ZRichard Qinrichard.qin.x@gmail.com2025-12-13T15:21:03Zurn:sha1:28fd88e0dd66728b22cd792deb5a1e8636f36ed3feat: Add initial Supervisor Mode Trap Handler2025-12-09T17:19:32ZRichard Qinrichard.qin.x@gmail.com2025-12-09T17:19:32Zurn:sha1:497e4a1b2f6f9181518e9887991c0464bd8f6bcf
Implement the initial mechanism for handling traps and exceptions in Supervisor Mode.
Set up the stvec Control and Status Register (CSR) to direct all S-Mode Traps (Interrupts and Exceptions) to a unified assembly entry point.
Implemented assembly code for saving and restoring the Trap Context (register state).
Provides the foundational framework necessary for future Timer Interrupts and System Calls.
The start of the project -- A MicroDOS2025-12-08T14:25:48ZRichard Qinrichard.qin.x@gmail.com2025-12-08T14:25:48Zurn:sha1:8cf8be522133548ee25fdcb0258ddf3950a68bcf
feat: Initial bare-metal RISC-V boot with UART