diff options
| -rw-r--r-- | na/arch/riscv/include/arch/cpu.h | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/na/arch/riscv/include/arch/cpu.h b/na/arch/riscv/include/arch/cpu.h index 644ae37..d16cf2d 100644 --- a/na/arch/riscv/include/arch/cpu.h +++ b/na/arch/riscv/include/arch/cpu.h @@ -22,6 +22,11 @@ #define SSTATUS_SPIE (1UL << 5) /* Supervisor Previous Interrupt Enable */ #define SSTATUS_SPP (1UL << 8) /* Supervisor Previous Privilege (0=U, 1=S) */ +/* RISC-V sie register bit definitions */ +#define SIE_SSIE (1UL << 1) /* Supervisor Software Interrupt Enable */ +#define SIE_STIE (1UL << 5) /* Supervisor Timer Interrupt Enable */ +#define SIE_SEIE (1UL << 9) /* Supervisor External Interrupt Enable */ + namespace arch::cpu { // Get current CPU ID (from tp register, set by entry.S) @@ -61,4 +66,14 @@ static inline uint64 read_time() { return val; } +// Enable timer interrupt in sie (sie.STIE = 1) +static inline void timer_intr_on() { + __asm__ volatile("csrs sie, %0" :: "r"(SIE_STIE)); +} + +// Disable timer interrupt in sie (sie.STIE = 0) +static inline void timer_intr_off() { + __asm__ volatile("csrc sie, %0" :: "r"(SIE_STIE)); +} + } // namespace arch::cpu |