| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | dev(device): implement VirtIO | Richard Qin | 2026-01-01 | 42 | -619/+1897 |
| | | | | | See dev log for detail | ||||
| * | dev: PILC implementation | Richard Qin | 2025-12-31 | 6 | -0/+94 |
| | | |||||
| * | dev log | Richard Qin | 2025-12-31 | 1 | -0/+37 |
| | | |||||
| * | dev:Refactor Memory Management and Process Management | Richard Qin | 2025-12-31 | 52 | -924/+2090 |
| | | |||||
| * | dev(spinlock): refactoring the implementation of locks | Richard Qin | 2025-12-30 | 4 | -116/+257 |
| | | |||||
| * | dev(pmm.h): refactor header file | Richard Qin | 2025-12-30 | 1 | -4/+44 |
| | | |||||
| * | feat(types): defined a type alias | Richard Qin | 2025-12-30 | 1 | -15/+20 |
| | | |||||
| * | Merge branch 'main' into feature/stdlib | Richard Qin | 2025-12-29 | 1 | -73/+115 |
| |\ | |||||
| | * | feat(README): Update README file | Richard Qin | 2025-12-29 | 1 | -73/+115 |
| | | | |||||
| * | | feat(stdlib): standard I/O Implementation | Richard Qin | 2025-12-28 | 5 | -0/+3146 |
| |/ | |||||
| * | fixed(vm): page allocation error | Richard Qin | 2025-12-28 | 3 | -1/+1 |
| | | |||||
| * | fixed(proc):Fix the page table mapping error during process fork | Richard Qin | 2025-12-28 | 5 | -5/+11 |
| | | |||||
| * | feat(syscall): implement functional sys_write using copyin for user console ↵ | Richard Qin | 2025-12-28 | 3 | -6/+24 |
| | | | | | output | ||||
| * | feat(user): add user-space build system and init process to test fork/wait | Richard Qin | 2025-12-28 | 16 | -16/+391 |
| | | |||||
| * | feat(syscall): Implement syscall dispatch and process lifecycle ↵ | Richard Qin | 2025-12-28 | 21 | -128/+633 |
| | | | | | (exit/wait/sleep) | ||||
| * | feat: Implement the first user program of the lume OS | Richard Qin | 2025-12-27 | 20 | -82/+593 |
| | | |||||
| * | feat: Encapsulates the low-level hardware details of the RISC-V ↵ | Richard Qin | 2025-12-25 | 1 | -0/+400 |
| | | | | | | | architecture, providing interfaces for the rest of the kernel to operate CPU registers and manage memory Copied from the xv-6 source code. | ||||
| * | Add the README to provide a detailed explanation of the project | Richard Qin | 2025-12-14 | 4 | -1/+95 |
| | | |||||
| * | feat: add preemptive scheduling, SBI timer support and FDT parser. | Richard Qin | 2025-12-13 | 23 | -62/+249 |
| | | |||||
| * | feat:Cooperative Multitasking | Richard Qin | 2025-12-11 | 15 | -52/+294 |
| | | |||||
| * | feat: Add initial Supervisor Mode Trap Handler | Richard Qin | 2025-12-10 | 12 | -17/+310 |
| | | | | | | | | | | | Implement the initial mechanism for handling traps and exceptions in Supervisor Mode. Set up the stvec Control and Status Register (CSR) to direct all S-Mode Traps (Interrupts and Exceptions) to a unified assembly entry point. Implemented assembly code for saving and restoring the Trap Context (register state). Provides the foundational framework necessary for future Timer Interrupts and System Calls. | ||||
| * | feat: Initial PMM implementation | Richard Qin | 2025-12-09 | 21 | -185/+376 |
| | | | | | | | Introduce the foundational Physical Memory Manager (PMM) and restructure the project for modularity. Implemented basic PMM and related memory management headers (mm/pmm.h, mm/vm.h). Updated Makefile and build process to support new modular structure. | ||||
| * | The start of the project -- A MicroDOS | Richard Qin | 2025-12-08 | 15 | -0/+307 |
| feat: Initial bare-metal RISC-V boot with UART | |||||
 |
index : lume | |
| A general-purpose operating system with Linux ABI compatibility |
| summaryrefslogtreecommitdiff |