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* Merge branch 'main' into feature/stdlibRichard Qin2025-12-291-73/+115
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| * feat(README): Update README fileRichard Qin2025-12-291-73/+115
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* | feat(stdlib): standard I/O ImplementationRichard Qin2025-12-285-0/+3146
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* fixed(vm): page allocation errorRichard Qin2025-12-283-1/+1
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* fixed(proc):Fix the page table mapping error during process forkRichard Qin2025-12-285-5/+11
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* feat(syscall): implement functional sys_write using copyin for user console ↵Richard Qin2025-12-283-6/+24
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* feat(user): add user-space build system and init process to test fork/waitRichard Qin2025-12-2816-16/+391
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* feat(syscall): Implement syscall dispatch and process lifecycle ↵Richard Qin2025-12-2821-128/+633
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* feat: Implement the first user program of the lume OSRichard Qin2025-12-2720-82/+593
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* feat: Encapsulates the low-level hardware details of the RISC-V ↵Richard Qin2025-12-251-0/+400
| | | | | | architecture, providing interfaces for the rest of the kernel to operate CPU registers and manage memory Copied from the xv-6 source code.
* Add the README to provide a detailed explanation of the projectRichard Qin2025-12-144-1/+95
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* feat: add preemptive scheduling, SBI timer support and FDT parser.Richard Qin2025-12-1323-62/+249
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* feat:Cooperative MultitaskingRichard Qin2025-12-1115-52/+294
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* feat: Add initial Supervisor Mode Trap HandlerRichard Qin2025-12-1012-17/+310
| | | | | | | | | | Implement the initial mechanism for handling traps and exceptions in Supervisor Mode. Set up the stvec Control and Status Register (CSR) to direct all S-Mode Traps (Interrupts and Exceptions) to a unified assembly entry point. Implemented assembly code for saving and restoring the Trap Context (register state). Provides the foundational framework necessary for future Timer Interrupts and System Calls.
* feat: Initial PMM implementationRichard Qin2025-12-0921-185/+376
| | | | | | Introduce the foundational Physical Memory Manager (PMM) and restructure the project for modularity. Implemented basic PMM and related memory management headers (mm/pmm.h, mm/vm.h). Updated Makefile and build process to support new modular structure.
* The start of the project -- A MicroDOSRichard Qin2025-12-0815-0/+307
feat: Initial bare-metal RISC-V boot with UART