| Commit message (Collapse) | Author | Age | Files | Lines |
| |
|
|
| |
lock-free programming requirements
|
| |
|
|
| |
formatting and linting
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
- Implement MMU hardware primitives for RISC-V SV39 in mmu.h
- Create trap vector control primitives in trap.h
- Define trap frame structure for RISC-V in trapframe.h
- Add assembly routines for context switching in swtch.S
- Implement trap vector entry/exit in trap_vector.S
- Introduce basic error number definitions in errno.h
- Provide placement new/delete operators in new.h
- Define kernel panic handler in panic.h and implement in panic.cc
- Establish basic type definitions in types.h
- Create the kernel main entry point in main.cc with global initialization
- Add synchronization primitives using spinlocks in spinlock.h and spinlock.cc
- Define per-CPU state tracking for interrupts in cpu_state.h
- Create a linker script for the kernel in linker.ld
- Update module makefiles for kernel and library components
|
| |
|
|
|
|
|
|
| |
spinlock documentation
- Introduced global initialization sequence documentation outlining the objectives, dependencies, core data structures, public APIs, concurrency contracts, error paths, and state machine for LumeOS.
- Created linker and entry documentation defining early memory layout and assembly startup sequence compatible with multiple bootloaders, including API specifications and error handling.
- Added spinlock documentation detailing the implementation of spinlocks, concurrency synchronization, memory ordering guarantees, and error handling mechanisms.
|
| | |
|
| | |
|
| |
|
|
| |
logging to exec syscalls
|
| |\
| |
| | |
Important: License changed from MIT to GPL.
|
| |/
|
|
| |
Rewrote the README based on the actual project.
|
| |\
| |
| | |
A basically complete operating system has been implemented
|
| |/
|
|
| |
fixed(file-system): fixed read and write bugs
|
| |\
| |
| | |
feat(file-system): implement read and write FAT32 File System and basic shell
|
| |/ |
|
| |\
| |
| |
| |
| | |
Rebuilt the system's underlying structure; it is now stable enough to merge.
The system now supports a read-only file system and has a simple shell implemented.
|
| | |
| |
| |
| |
| |
| |
| |
| |
| |
| | |
Summary:
- Fixed an integer arithmetic error in malloc() where 'nunits' was initialized to 0, causing incorrect heap sizing.
- This bug caused malloc to return pointers pointing to unmapped memory pages, leading to Store Page Fault (scause 15) at process boundaries.
- Switched memory allocator logic to use byte-based size calculation instead of K&R style units to prevent off-by-one errors.
Improvements:
- Shell now starts successfully without segfaults.
|
| | |
| |
| |
| | |
please see the log for detail.
|
| | | |
|
| | |
| |
| |
| | |
See dev log for detail
|
| | | |
|
| | | |
|
| | | |
|
| | | |
|
| | | |
|
| | | |
|
| | |\
| |/
|/| |
|
| | | |
|
| |/ |
|
| | |
|
| | |
|
| |
|
|
| |
output
|
| | |
|
| |
|
|
| |
(exit/wait/sleep)
|
| | |
|
| |
|
|
|
|
| |
architecture, providing interfaces for the rest of the kernel to operate CPU registers and manage memory
Copied from the xv-6 source code.
|
| | |
|
| | |
|
| | |
|
| |
|
|
|
|
|
|
|
|
| |
Implement the initial mechanism for handling traps and exceptions in Supervisor Mode.
Set up the stvec Control and Status Register (CSR) to direct all S-Mode Traps (Interrupts and Exceptions) to a unified assembly entry point.
Implemented assembly code for saving and restoring the Trap Context (register state).
Provides the foundational framework necessary for future Timer Interrupts and System Calls.
|
| |
|
|
|
|
| |
Introduce the foundational Physical Memory Manager (PMM) and restructure the project for modularity.
Implemented basic PMM and related memory management headers (mm/pmm.h, mm/vm.h).
Updated Makefile and build process to support new modular structure.
|
|
|
feat: Initial bare-metal RISC-V boot with UART
|