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* feat: add preemptive scheduling, SBI timer support and FDT parser.Richard Qin2025-12-1323-62/+249
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* feat:Cooperative MultitaskingRichard Qin2025-12-1115-52/+294
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* feat: Add initial Supervisor Mode Trap HandlerRichard Qin2025-12-1012-17/+310
| | | | | | | | | | Implement the initial mechanism for handling traps and exceptions in Supervisor Mode. Set up the stvec Control and Status Register (CSR) to direct all S-Mode Traps (Interrupts and Exceptions) to a unified assembly entry point. Implemented assembly code for saving and restoring the Trap Context (register state). Provides the foundational framework necessary for future Timer Interrupts and System Calls.
* feat: Initial PMM implementationRichard Qin2025-12-0921-185/+376
| | | | | | Introduce the foundational Physical Memory Manager (PMM) and restructure the project for modularity. Implemented basic PMM and related memory management headers (mm/pmm.h, mm/vm.h). Updated Makefile and build process to support new modular structure.
* The start of the project -- A MicroDOSRichard Qin2025-12-0815-0/+307
feat: Initial bare-metal RISC-V boot with UART