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See dev log for detail
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Implement the initial mechanism for handling traps and exceptions in Supervisor Mode.
Set up the stvec Control and Status Register (CSR) to direct all S-Mode Traps (Interrupts and Exceptions) to a unified assembly entry point.
Implemented assembly code for saving and restoring the Trap Context (register state).
Provides the foundational framework necessary for future Timer Interrupts and System Calls.
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Introduce the foundational Physical Memory Manager (PMM) and restructure the project for modularity.
Implemented basic PMM and related memory management headers (mm/pmm.h, mm/vm.h).
Updated Makefile and build process to support new modular structure.
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feat: Initial bare-metal RISC-V boot with UART
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