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* feat:Cooperative MultitaskingRichard Qin2025-12-111-0/+0
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* feat: Add initial Supervisor Mode Trap HandlerRichard Qin2025-12-102-0/+0
Implement the initial mechanism for handling traps and exceptions in Supervisor Mode. Set up the stvec Control and Status Register (CSR) to direct all S-Mode Traps (Interrupts and Exceptions) to a unified assembly entry point. Implemented assembly code for saving and restoring the Trap Context (register state). Provides the foundational framework necessary for future Timer Interrupts and System Calls.