| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | feat: implement FDT-based memory discovery and add comprehensive debug ↵ | Richard Qin | 2026-04-14 | 1 | -2/+6 |
| | | | | | logging to exec syscalls | ||||
| * | Important: License changed from MIT to GPL. | Richard Qin | 2026-01-05 | 4 | -0/+20 |
| | | | | | Rewrote the README based on the actual project. | ||||
| * | feat(file-system): implement read and write FAT32 File System and basic shell | Richard Qin | 2026-01-04 | 2 | -8/+8 |
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| * | dev(file-system): establish VFS and Read-only FAT32 File System | Richard Qin | 2026-01-02 | 1 | -0/+1 |
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| * | dev(device): implement VirtIO | Richard Qin | 2026-01-01 | 3 | -2/+128 |
| | | | | | See dev log for detail | ||||
| * | dev: PILC implementation | Richard Qin | 2025-12-31 | 1 | -0/+17 |
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| * | dev:Refactor Memory Management and Process Management | Richard Qin | 2025-12-31 | 1 | -4/+7 |
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| * | feat: Add initial Supervisor Mode Trap Handler | Richard Qin | 2025-12-10 | 1 | -0/+2 |
| | | | | | | | | | | | Implement the initial mechanism for handling traps and exceptions in Supervisor Mode. Set up the stvec Control and Status Register (CSR) to direct all S-Mode Traps (Interrupts and Exceptions) to a unified assembly entry point. Implemented assembly code for saving and restoring the Trap Context (register state). Provides the foundational framework necessary for future Timer Interrupts and System Calls. | ||||
| * | The start of the project -- A MicroDOS | Richard Qin | 2025-12-08 | 1 | -0/+7 |
| feat: Initial bare-metal RISC-V boot with UART | |||||
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index : lume | |
| A general-purpose operating system with Linux ABI compatibility |
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