| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | dev:Refactor Memory Management and Process Management | Richard Qin | 2025-12-31 | 11 | -86/+162 |
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| * | dev(spinlock): refactoring the implementation of locks | Richard Qin | 2025-12-30 | 2 | -15/+61 |
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| * | dev(pmm.h): refactor header file | Richard Qin | 2025-12-30 | 1 | -4/+44 |
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| * | feat(user): add user-space build system and init process to test fork/wait | Richard Qin | 2025-12-28 | 1 | -1/+3 |
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| * | feat(syscall): Implement syscall dispatch and process lifecycle ↵ | Richard Qin | 2025-12-28 | 3 | -2/+56 |
| | | | | | (exit/wait/sleep) | ||||
| * | feat: Implement the first user program of the lume OS | Richard Qin | 2025-12-27 | 4 | -15/+28 |
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| * | feat: Encapsulates the low-level hardware details of the RISC-V ↵ | Richard Qin | 2025-12-25 | 1 | -0/+400 |
| | | | | | | | architecture, providing interfaces for the rest of the kernel to operate CPU registers and manage memory Copied from the xv-6 source code. | ||||
| * | feat: add preemptive scheduling, SBI timer support and FDT parser. | Richard Qin | 2025-12-13 | 1 | -0/+7 |
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| * | feat:Cooperative Multitasking | Richard Qin | 2025-12-11 | 2 | -0/+62 |
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| * | feat: Add initial Supervisor Mode Trap Handler | Richard Qin | 2025-12-10 | 1 | -0/+50 |
| | | | | | | | | | | | Implement the initial mechanism for handling traps and exceptions in Supervisor Mode. Set up the stvec Control and Status Register (CSR) to direct all S-Mode Traps (Interrupts and Exceptions) to a unified assembly entry point. Implemented assembly code for saving and restoring the Trap Context (register state). Provides the foundational framework necessary for future Timer Interrupts and System Calls. | ||||
| * | feat: Initial PMM implementation | Richard Qin | 2025-12-09 | 2 | -0/+34 |
| Introduce the foundational Physical Memory Manager (PMM) and restructure the project for modularity. Implemented basic PMM and related memory management headers (mm/pmm.h, mm/vm.h). Updated Makefile and build process to support new modular structure. | |||||
