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* feat(syscall): Implement syscall dispatch and process lifecycle ↵Richard Qin2025-12-281-17/+18
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* feat: Implement the first user program of the lume OSRichard Qin2025-12-273-5/+153
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* feat: add preemptive scheduling, SBI timer support and FDT parser.Richard Qin2025-12-131-2/+1
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* feat:Cooperative MultitaskingRichard Qin2025-12-111-1/+5
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* feat: Add initial Supervisor Mode Trap HandlerRichard Qin2025-12-102-0/+210
Implement the initial mechanism for handling traps and exceptions in Supervisor Mode. Set up the stvec Control and Status Register (CSR) to direct all S-Mode Traps (Interrupts and Exceptions) to a unified assembly entry point. Implemented assembly code for saving and restoring the Trap Context (register state). Provides the foundational framework necessary for future Timer Interrupts and System Calls.