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* dev(device): implement VirtIORichard Qin2026-01-0113-231/+781
| | | | See dev log for detail
* dev: PILC implementationRichard Qin2025-12-312-0/+77
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* dev:Refactor Memory Management and Process ManagementRichard Qin2025-12-3113-650/+1461
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* dev(spinlock): refactoring the implementation of locksRichard Qin2025-12-302-101/+196
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* fixed(vm): page allocation errorRichard Qin2025-12-281-1/+1
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* fixed(proc):Fix the page table mapping error during process forkRichard Qin2025-12-282-5/+11
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* feat(syscall): implement functional sys_write using copyin for user console ↵Richard Qin2025-12-281-6/+24
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* feat(user): add user-space build system and init process to test fork/waitRichard Qin2025-12-285-9/+106
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* feat(syscall): Implement syscall dispatch and process lifecycle ↵Richard Qin2025-12-288-126/+564
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* feat: Implement the first user program of the lume OSRichard Qin2025-12-277-66/+559
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* Add the README to provide a detailed explanation of the projectRichard Qin2025-12-141-1/+1
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* feat: add preemptive scheduling, SBI timer support and FDT parser.Richard Qin2025-12-139-59/+237
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* feat:Cooperative MultitaskingRichard Qin2025-12-116-52/+232
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* feat: Add initial Supervisor Mode Trap HandlerRichard Qin2025-12-104-16/+255
| | | | | | | | | | Implement the initial mechanism for handling traps and exceptions in Supervisor Mode. Set up the stvec Control and Status Register (CSR) to direct all S-Mode Traps (Interrupts and Exceptions) to a unified assembly entry point. Implemented assembly code for saving and restoring the Trap Context (register state). Provides the foundational framework necessary for future Timer Interrupts and System Calls.
* feat: Initial PMM implementationRichard Qin2025-12-094-20/+253
| | | | | | Introduce the foundational Physical Memory Manager (PMM) and restructure the project for modularity. Implemented basic PMM and related memory management headers (mm/pmm.h, mm/vm.h). Updated Makefile and build process to support new modular structure.
* The start of the project -- A MicroDOSRichard Qin2025-12-083-0/+105
feat: Initial bare-metal RISC-V boot with UART