From 6907a90418ba856ff9331e6b4ba5d26b76034c2d Mon Sep 17 00:00:00 2001 From: Richard Qin Date: Sat, 2 May 2026 23:31:46 +0800 Subject: feat: add RISC-V configuration and memory management enhancements Co-authored-by: Copilot --- na/arch/riscv/module.mk | 3 +++ 1 file changed, 3 insertions(+) (limited to 'na/arch/riscv/module.mk') diff --git a/na/arch/riscv/module.mk b/na/arch/riscv/module.mk index 154ae77..9635fea 100644 --- a/na/arch/riscv/module.mk +++ b/na/arch/riscv/module.mk @@ -1,5 +1,8 @@ # arch/riscv/module.mk SRCS_CC += arch/riscv/mm/pmap.cc +SRCS_CC += arch/riscv/config.cc +SRCS_CC += arch/riscv/trap/trap_md.cc +SRCS_CC += arch/riscv/lib/random.cc SRCS_S += arch/riscv/boot/entry.S SRCS_S += arch/riscv/trap/swtch.S SRCS_S += arch/riscv/trap/trap_vector.S -- cgit v1.2.3