From 8cf8be522133548ee25fdcb0258ddf3950a68bcf Mon Sep 17 00:00:00 2001
From: Richard Qin <richard.qin.x@gmail.com>
Date: Mon, 8 Dec 2025 22:25:48 +0800
Subject: The start of the project -- A MicroDOS feat: Initial bare-metal
 RISC-V boot with UART

---
 src/drivers/uart.cc | 57 +++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 57 insertions(+)
 create mode 100644 src/drivers/uart.cc

(limited to 'src/drivers/uart.cc')

diff --git a/src/drivers/uart.cc b/src/drivers/uart.cc
new file mode 100644
index 0000000..758abd9
--- /dev/null
+++ b/src/drivers/uart.cc
@@ -0,0 +1,57 @@
+#include "drivers/uart.h"
+#include "common/types.h"
+
+#define UART0_BASE          0x10000000L
+
+#define UART_RBR            0x00 // Receiver Buffer Register (Read)
+#define UART_THR            0x00 // Transmitter Holding Register (Write)
+#define UART_IER            0x01 // Interrupt Enable Register
+#define UART_FCR            0x02 // FIFO Control Register
+#define UART_LCR            0x03 // Line Control Register
+#define UART_LSR            0x05 // Line Status Register
+
+#define UART_LSR_RX_READY   0x01
+#define UART_LSR_TX_EMPTY   0x20
+
+namespace Drivers{
+    inline volatile uint8_t &reg(uint32_t offset)
+    {
+        return *reinterpret_cast<volatile uint8_t *>(UART0_BASE + offset);
+    }
+
+    void uart_init()
+    {
+        reg(UART_IER) = 0x00;
+
+        reg(UART_LCR) = 0x80;
+        reg(0x00) = 0x03;
+        reg(0x01) = 0x00;
+
+        reg(UART_LCR) = 0x03;
+
+        reg(UART_FCR) = 0x07; // Enable FIFO, clear TX/RX queues
+    }
+
+    void uart_putc(char c)
+    {
+        if (c == '\n')
+        {
+            uart_putc('\r');
+        }
+
+        while ((reg(UART_LSR) & UART_LSR_TX_EMPTY) == 0)
+        {
+
+        }
+
+        reg(UART_THR) = c;
+    }
+
+    void uart_puts(const char *s)
+    {
+        while (*s)
+        {
+            uart_putc(*s++);
+        }
+    }
+}
\ No newline at end of file
-- 
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