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<title>rcc-project/backend/include/rcc/CodeGen/InstructionDescriptor.h, branch master</title>
<subtitle>An optimizing compiler for C.
</subtitle>
<id>https://git.richardqin.org/rcc-project/atom?h=master</id>
<link rel='self' href='https://git.richardqin.org/rcc-project/atom?h=master'/>
<link rel='alternate' type='text/html' href='https://git.richardqin.org/rcc-project/'/>
<updated>2026-08-26T09:38:21Z</updated>
<entry>
<title>[CodeGen] Implement RISC-V finalize-isel</title>
<updated>2026-08-26T09:38:21Z</updated>
<author>
<name>Richard-Qin-X</name>
<email>richard.qin.001@gmail.com</email>
</author>
<published>2026-08-26T09:38:21Z</published>
<link rel='alternate' type='text/html' href='https://git.richardqin.org/rcc-project/commit/?id=36c4344ddf1866005c62910166ca077bf2e8f62e'/>
<id>urn:sha1:36c4344ddf1866005c62910166ca077bf2e8f62e</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[CodeGen] Remove unsupported pre-PEI pseudo expansion</title>
<updated>2026-08-19T09:16:32Z</updated>
<author>
<name>Richard-Qin-X</name>
<email>richard.qin.001@gmail.com</email>
</author>
<published>2026-08-19T09:16:32Z</published>
<link rel='alternate' type='text/html' href='https://git.richardqin.org/rcc-project/commit/?id=f7df62b40fd06585bb8c93d001f90e37d3aea3c2'/>
<id>urn:sha1:f7df62b40fd06585bb8c93d001f90e37d3aea3c2</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[RISCV][GlobalISel] Select and expand global addresses</title>
<updated>2026-08-18T20:27:41Z</updated>
<author>
<name>Richard-Qin-X</name>
<email>richard.qin.001@gmail.com</email>
</author>
<published>2026-08-18T20:27:41Z</published>
<link rel='alternate' type='text/html' href='https://git.richardqin.org/rcc-project/commit/?id=307fc0961972ac5264d6f3459978fbec95cad3a9'/>
<id>urn:sha1:307fc0961972ac5264d6f3459978fbec95cad3a9</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[CodeGen] Match LLVM Legalizer ownership</title>
<updated>2026-08-13T20:33:41Z</updated>
<author>
<name>Richard-Qin-X</name>
<email>richard.qin.001@gmail.com</email>
</author>
<published>2026-08-13T20:33:41Z</published>
<link rel='alternate' type='text/html' href='https://git.richardqin.org/rcc-project/commit/?id=8be4d04455f70892a94d1e0798e266c948b4750a'/>
<id>urn:sha1:8be4d04455f70892a94d1e0798e266c948b4750a</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[CodeGen] Unify scalar low-level types</title>
<updated>2026-08-13T15:55:38Z</updated>
<author>
<name>Richard-Qin-X</name>
<email>richard.qin.001@gmail.com</email>
</author>
<published>2026-08-13T15:55:38Z</published>
<link rel='alternate' type='text/html' href='https://git.richardqin.org/rcc-project/commit/?id=aa69e15c6909c3b162b15f5326f0a72ba9bb7163'/>
<id>urn:sha1:aa69e15c6909c3b162b15f5326f0a72ba9bb7163</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[CodeGen] Match LLVM branch relaxation semantics</title>
<updated>2026-08-13T11:38:37Z</updated>
<author>
<name>Richard-Qin-X</name>
<email>richard.qin.001@gmail.com</email>
</author>
<published>2026-08-13T11:38:37Z</published>
<link rel='alternate' type='text/html' href='https://git.richardqin.org/rcc-project/commit/?id=98cae0e8835a1eb8fcb0e43870c04ed934cc51ac'/>
<id>urn:sha1:98cae0e8835a1eb8fcb0e43870c04ed934cc51ac</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[CodeGen] Implement machine optimization and scheduling</title>
<updated>2026-08-09T09:03:19Z</updated>
<author>
<name>Richard-Qin-X</name>
<email>richard.qin.001@gmail.com</email>
</author>
<published>2026-08-09T09:03:19Z</published>
<link rel='alternate' type='text/html' href='https://git.richardqin.org/rcc-project/commit/?id=495c675771f43cfa12ab7a426a538be72fec1805'/>
<id>urn:sha1:495c675771f43cfa12ab7a426a538be72fec1805</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[CodeGen] Implement machine SSA exit</title>
<updated>2026-08-07T20:14:34Z</updated>
<author>
<name>Richard-Qin-X</name>
<email>richard.qin.001@gmail.com</email>
</author>
<published>2026-08-07T20:14:34Z</published>
<link rel='alternate' type='text/html' href='https://git.richardqin.org/rcc-project/commit/?id=77884c967d1cbc48afcbaef7e5a35adcb3c5da1b'/>
<id>urn:sha1:77884c967d1cbc48afcbaef7e5a35adcb3c5da1b</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[RISCV] Complete RV64GC instruction description</title>
<updated>2026-08-07T14:03:11Z</updated>
<author>
<name>Richard-Qin-X</name>
<email>richard.qin.001@gmail.com</email>
</author>
<published>2026-08-07T14:03:11Z</published>
<link rel='alternate' type='text/html' href='https://git.richardqin.org/rcc-project/commit/?id=3e15bfd7b075209ec3b65d30d0611e060f6fbb77'/>
<id>urn:sha1:3e15bfd7b075209ec3b65d30d0611e060f6fbb77</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[MIR] Complete document parsing and printing</title>
<updated>2026-08-06T17:27:41Z</updated>
<author>
<name>Richard-Qin-X</name>
<email>richard.qin.001@gmail.com</email>
</author>
<published>2026-08-06T17:27:41Z</published>
<link rel='alternate' type='text/html' href='https://git.richardqin.org/rcc-project/commit/?id=76d89700953ddd81cf31ab8f260eddf67e93aa85'/>
<id>urn:sha1:76d89700953ddd81cf31ab8f260eddf67e93aa85</id>
<content type='text'>
Implement the single LLVM-compatible MIR document path with structured\nembedded-IR references, YAML mappings, constants, and deterministic printing.\n\nKeep pointer LLT widths DataLayout-derived, reject layout-dependent output\nwhen embedded IR is omitted, and record the fixed-baseline compatibility\ncontract and regression coverage.
</content>
</entry>
</feed>
