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<title>rcc-project/backend/include/rcc/CodeGen/MachineFunctionCloner.h, branch master</title>
<subtitle>An optimizing compiler for C.
</subtitle>
<id>https://git.richardqin.org/rcc-project/atom?h=master</id>
<link rel='self' href='https://git.richardqin.org/rcc-project/atom?h=master'/>
<link rel='alternate' type='text/html' href='https://git.richardqin.org/rcc-project/'/>
<updated>2026-08-01T08:07:24Z</updated>
<entry>
<title>[CodeGen] Add target register descriptions</title>
<updated>2026-08-01T08:07:24Z</updated>
<author>
<name>Richard-Qin-X</name>
<email>richard.qin.001@gmail.com</email>
</author>
<published>2026-08-01T08:07:24Z</published>
<link rel='alternate' type='text/html' href='https://git.richardqin.org/rcc-project/commit/?id=924dcd36ebed84f04729de05ec08b311a36a04c1'/>
<id>urn:sha1:924dcd36ebed84f04729de05ec08b311a36a04c1</id>
<content type='text'>
Introduce an immutable register topology for units, subregisters, classes, banks, and preserved masks. Bind instruction descriptors to this topology through TargetDescription so builders, cloning, and verification share one target-aware contract. Add the test-only TestTarget model and positive and negative target fact coverage.
</content>
</entry>
<entry>
<title>[CodeGen] Add target state and compilation status</title>
<updated>2026-08-01T06:50:04Z</updated>
<author>
<name>Richard-Qin-X</name>
<email>richard.qin.001@gmail.com</email>
</author>
<published>2026-08-01T06:50:04Z</published>
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<id>urn:sha1:cfdbcc469f9691bd9dce3b0b86982a63d86ca6b7</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[CodeGen] Add explicit MachineFunction cloning</title>
<updated>2026-08-01T05:37:56Z</updated>
<author>
<name>Richard-Qin-X</name>
<email>richard.qin.001@gmail.com</email>
</author>
<published>2026-08-01T05:37:56Z</published>
<link rel='alternate' type='text/html' href='https://git.richardqin.org/rcc-project/commit/?id=786ccc115f851962f3a7d234846a50f4af8aad64'/>
<id>urn:sha1:786ccc115f851962f3a7d234846a50f4af8aad64</id>
<content type='text'>
Deep-clone the live MachineIR graph with deterministic identity maps while rebuilding CFG, def-use, ties, register configuration, and memory operand ownership. Verify both source and destination and omit detached arena history.
</content>
</entry>
</feed>
