rcc-project/backend/include/rcc/CodeGen/MachineMemOperand.h, branch masterAn optimizing compiler for C.
https://git.richardqin.org/rcc-project/atom?h=master2026-08-13T15:55:38Z[CodeGen] Unify scalar low-level types2026-08-13T15:55:38ZRichard-Qin-Xrichard.qin.001@gmail.com2026-08-13T15:55:38Zurn:sha1:aa69e15c6909c3b162b15f5326f0a72ba9bb7163[IR] Split LL parsing, assembly writing, and data layout2026-08-13T04:55:12ZRichard-Qin-Xrichard.qin.001@gmail.com2026-08-13T04:55:12Zurn:sha1:fde3e045d4dcc5c404cb4216389e18b0e720b8e0[MIR] Accept fixed-baseline LLVM syntax2026-08-11T09:37:42ZRichard-Qin-Xrichard.qin.001@gmail.com2026-08-11T09:37:42Zurn:sha1:6a7b083f322f4ac47e58cbf9d4d5fd4d1f6fecd0[MIR] Add machine instruction parser and printer2026-08-03T21:34:15ZRichard-Qin-Xrichard.qin.001@gmail.com2026-08-03T21:34:15Zurn:sha1:183e2354e9fdd107be420cbb185c1d239434aa48
Parse MachineFunction bodies in two passes and serialize the same MachineIR model in complete or readable form. Extend instruction attachments and memory operands required by the fixed LLVM MIR grammar, and cover deterministic parse-print round trips.
[CodeGen] Add target MIR text schema2026-08-03T11:24:30ZRichard-Qin-Xrichard.qin.001@gmail.com2026-08-03T11:24:30Zurn:sha1:432efe39315ed5ad0162f9c08dbf10941bc21dc1[CodeGen] Add MIR function and block attributes2026-08-01T09:36:40ZRichard-Qin-Xrichard.qin.001@gmail.com2026-08-01T09:36:40Zurn:sha1:787f3a7a20958bfa6f231abccc617f4d8de25c4d[CodeGen] Build the core MachineIR object model2026-07-31T21:27:13ZRichard-Qin-Xrichard.qin.001@gmail.com2026-07-31T21:27:13Zurn:sha1:c759cebef15bdac2ef160065efd116fe6ed540a7
Add arena-owned, address-stable MachineFunction, MachineBasicBlock, and MachineInstr nodes with intrusive layout and instruction lists. Model every required MachineOperand category, reciprocal ties, source state, and immutable per-instruction memory references.
Implement physical and virtual register def-use chains whose back-links survive operand vector moves, plus vreg properties, tombstones, live-ins, reserved registers, and atomic CFG updates. Exercise ownership, reallocation, unlink/relink, cross-function rejection, and sanitizer paths.
[CodeGen] Add machine IR value semantics2026-07-31T21:01:57ZRichard-Qin-Xrichard.qin.001@gmail.com2026-07-31T21:01:57Zurn:sha1:e2505772ab260c79d0075728082c907a90dab7ca
Add strongly typed machine indices, lane masks, instruction flags, fixed-point branch probabilities, and preserved-register masks.
Model immutable machine memory operands with explicit base identity, size, alignment, address space, alias information, and validated atomic operation and ordering rules. Cover normal, boundary, and invalid combinations in standalone tests.