rcc-project/backend/include/rcc/CodeGen/MachineRegisterInfo.h, branch master
An optimizing compiler for C.
https://git.richardqin.org/rcc-project/atom?h=master
2026-08-14T12:35:54Z
[GlobalISel] Match LLVM legalization value tracking
2026-08-14T12:35:54Z
Richard-Qin-X
richard.qin.001@gmail.com
2026-08-14T12:35:54Z
urn:sha1:97e5fbaa55b4672db36123c2425d05a4738452ab
[CodeGen] Match LLVM Legalizer ownership
2026-08-13T20:33:41Z
Richard-Qin-X
richard.qin.001@gmail.com
2026-08-13T20:33:41Z
urn:sha1:8be4d04455f70892a94d1e0798e266c948b4750a
[CodeGen] Unify scalar low-level types
2026-08-13T15:55:38Z
Richard-Qin-X
richard.qin.001@gmail.com
2026-08-13T15:55:38Z
urn:sha1:aa69e15c6909c3b162b15f5326f0a72ba9bb7163
[RISCV] Match LLVM register bank mappings
2026-08-13T11:04:49Z
Richard-Qin-X
richard.qin.001@gmail.com
2026-08-13T11:04:49Z
urn:sha1:1ef9d699d3160a9f79e89f423352fbb8d43e70d7
[MIR] Accept fixed-baseline LLVM syntax
2026-08-11T09:37:42Z
Richard-Qin-X
richard.qin.001@gmail.com
2026-08-11T09:37:42Z
urn:sha1:6a7b083f322f4ac47e58cbf9d4d5fd4d1f6fecd0
[CodeGen] Complete register allocation infrastructure
2026-08-08T20:40:17Z
Richard-Qin-X
richard.qin.001@gmail.com
2026-08-08T20:40:17Z
urn:sha1:e5fdceb9b869f010a2a75638fd38aaf1867f3008
[CodeGen] Add target MIR text schema
2026-08-03T11:24:30Z
Richard-Qin-X
richard.qin.001@gmail.com
2026-08-03T11:24:30Z
urn:sha1:432efe39315ed5ad0162f9c08dbf10941bc21dc1
[CodeGen] Add strict MachineIR verification
2026-08-01T05:24:09Z
Richard-Qin-X
richard.qin.001@gmail.com
2026-08-01T05:24:09Z
urn:sha1:19d8e4f562a8583b002dbaa837ec0083e7768a4f
Verify arena catalogs, intrusive layouts, reciprocal CFG edges, operand ownership, exact def-use coverage, instruction descriptors, pseudo deadlines, and MachineFunctionProperties. Preserve monotonic-arena history while rejecting detached objects that retain live state.
[CodeGen] Build the core MachineIR object model
2026-07-31T21:27:13Z
Richard-Qin-X
richard.qin.001@gmail.com
2026-07-31T21:27:13Z
urn:sha1:c759cebef15bdac2ef160065efd116fe6ed540a7
Add arena-owned, address-stable MachineFunction, MachineBasicBlock, and MachineInstr nodes with intrusive layout and instruction lists. Model every required MachineOperand category, reciprocal ties, source state, and immutable per-instruction memory references.
Implement physical and virtual register def-use chains whose back-links survive operand vector moves, plus vreg properties, tombstones, live-ins, reserved registers, and atomic CFG updates. Exercise ownership, reallocation, unlink/relink, cross-function rejection, and sanitizer paths.