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<title>rcc-project/backend/include/rcc/CodeGen/TargetDescription.h, branch master</title>
<subtitle>An optimizing compiler for C.
</subtitle>
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<updated>2026-08-14T20:48:16Z</updated>
<entry>
<title>[GlobalISel] Lower stack operations</title>
<updated>2026-08-14T20:48:16Z</updated>
<author>
<name>Richard-Qin-X</name>
<email>richard.qin.001@gmail.com</email>
</author>
<published>2026-08-14T20:48:16Z</published>
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<id>urn:sha1:32a365a2dc0096b4421fb3947b32d971b7f34c40</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[GlobalISel] Match LLVM legalization value tracking</title>
<updated>2026-08-14T12:35:54Z</updated>
<author>
<name>Richard-Qin-X</name>
<email>richard.qin.001@gmail.com</email>
</author>
<published>2026-08-14T12:35:54Z</published>
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<id>urn:sha1:97e5fbaa55b4672db36123c2425d05a4738452ab</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[CodeGen] Implement machine SSA exit</title>
<updated>2026-08-07T20:14:34Z</updated>
<author>
<name>Richard-Qin-X</name>
<email>richard.qin.001@gmail.com</email>
</author>
<published>2026-08-07T20:14:34Z</published>
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<id>urn:sha1:77884c967d1cbc48afcbaef7e5a35adcb3c5da1b</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[CodeGen] Add target MIR text schema</title>
<updated>2026-08-03T11:24:30Z</updated>
<author>
<name>Richard-Qin-X</name>
<email>richard.qin.001@gmail.com</email>
</author>
<published>2026-08-03T11:24:30Z</published>
<link rel='alternate' type='text/html' href='https://git.richardqin.org/rcc-project/commit/?id=432efe39315ed5ad0162f9c08dbf10941bc21dc1'/>
<id>urn:sha1:432efe39315ed5ad0162f9c08dbf10941bc21dc1</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[CodeGen] Add target register descriptions</title>
<updated>2026-08-01T08:07:24Z</updated>
<author>
<name>Richard-Qin-X</name>
<email>richard.qin.001@gmail.com</email>
</author>
<published>2026-08-01T08:07:24Z</published>
<link rel='alternate' type='text/html' href='https://git.richardqin.org/rcc-project/commit/?id=924dcd36ebed84f04729de05ec08b311a36a04c1'/>
<id>urn:sha1:924dcd36ebed84f04729de05ec08b311a36a04c1</id>
<content type='text'>
Introduce an immutable register topology for units, subregisters, classes, banks, and preserved masks. Bind instruction descriptors to this topology through TargetDescription so builders, cloning, and verification share one target-aware contract. Add the test-only TestTarget model and positive and negative target fact coverage.
</content>
</entry>
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