rcc-project/backend/include/rcc/Target/RISCV/RISCVTarget.h, branch master

rcc-project/backend/include/rcc/Target/RISCV/RISCVTarget.h, branch master An optimizing compiler for C. https://git.richardqin.org/rcc-project/atom?h=master 2026-08-11T12:26:56Z [RISCV] Add LP64 calling-convention facts 2026-08-11T12:26:56Z Richard-Qin-X richard.qin.001@gmail.com 2026-08-11T12:26:56Z urn:sha1:38626ed37c9ea78c76c12dae4806b750881fd910 [MC] Implement RV64GC object emission 2026-08-09T14:05:14Z Richard-Qin-X richard.qin.001@gmail.com 2026-08-09T14:05:14Z urn:sha1:3a57627e59ba18b6f9f9aae7bb60c390c0d3575a [RISCV] Complete RV64GC instruction description 2026-08-07T14:03:11Z Richard-Qin-X richard.qin.001@gmail.com 2026-08-07T14:03:11Z urn:sha1:3e15bfd7b075209ec3b65d30d0611e060f6fbb77 [RISCV] Add generated RV64GC register description 2026-08-06T18:15:09Z Richard-Qin-X richard.qin.001@gmail.com 2026-08-06T18:15:09Z urn:sha1:e16de95dce32f077361577377d5c52fc4ad78339 Add an RCC-owned build-time target description generator and the initial RV64GC register model. Keep ABI aliases separate from canonical MIR register spelling.