rcc-project/backend/include/rcc/Target/RISCV, branch master

rcc-project/backend/include/rcc/Target/RISCV, branch master An optimizing compiler for C. https://git.richardqin.org/rcc-project/atom?h=master 2026-08-28T10:51:10Z [CodeGen] Add target machine registry 2026-08-28T10:51:10Z Richard-Qin-X richard.qin.001@gmail.com 2026-08-28T10:51:10Z urn:sha1:f89d528efc0228c049c2867dcba886a56bac8619 [CodeGen] Separate assembly emission ownership 2026-08-28T06:25:42Z Richard-Qin-X richard.qin.001@gmail.com 2026-08-28T06:25:42Z urn:sha1:6889b82a5c9ecc6bd178760c66653d7af0121162 [CodeGen] Implement RISC-V machine outlining 2026-08-24T18:21:25Z Richard-Qin-X richard.qin.001@gmail.com 2026-08-24T18:21:25Z urn:sha1:71988f9818677df0d90b19d4bb770ac8a6116e62 [RISCV] Implement Zcmp move merging 2026-08-24T17:43:04Z Richard-Qin-X richard.qin.001@gmail.com 2026-08-24T17:43:04Z urn:sha1:9e89d1d718977749ca798b27b7ad45e1781602c2 [RISCV] Match LLVM compressed stack frame lowering 2026-08-24T10:27:25Z Richard-Qin-X richard.qin.001@gmail.com 2026-08-24T10:27:25Z urn:sha1:f430936038432e90b2d70e08ac51620931651450 [RISCV] Match LLVM emergency spill layout 2026-08-24T09:30:29Z Richard-Qin-X richard.qin.001@gmail.com 2026-08-24T09:30:29Z urn:sha1:81afb6570000472c182e5b1f540f69382602aaad [RISCV] Match LLVM frame lowering semantics 2026-08-24T08:37:25Z Richard-Qin-X richard.qin.001@gmail.com 2026-08-24T08:37:25Z urn:sha1:540c73a2f450af3d0aec6e039fab054471efdbb1 [CodeGen] Generate RISC-V macro fusion rules 2026-08-22T10:49:08Z Richard-Qin-X richard.qin.001@gmail.com 2026-08-22T10:49:08Z urn:sha1:8a4bb6e3b0bffa0ed79b51347b12ee4293b622a7 [RISCV][GlobalISel] Select and expand global addresses 2026-08-18T20:27:41Z Richard-Qin-X richard.qin.001@gmail.com 2026-08-18T20:27:41Z urn:sha1:307fc0961972ac5264d6f3459978fbec95cad3a9 [RISCV][GlobalISel] Generate integer extension selections 2026-08-16T18:22:27Z Richard-Qin-X richard.qin.001@gmail.com 2026-08-16T18:22:27Z urn:sha1:f6a3a06de3d32eaeba1f3c8bbc5faa5ffaeb1128