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<title>rcc-project/backend/lib/CodeGen/GenericOpcodes.cpp, branch master</title>
<subtitle>An optimizing compiler for C.
</subtitle>
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<updated>2026-08-14T20:23:23Z</updated>
<entry>
<title>[RISCV][GlobalISel] Legalize scalar bit count operations</title>
<updated>2026-08-14T20:23:23Z</updated>
<author>
<name>Richard-Qin-X</name>
<email>richard.qin.001@gmail.com</email>
</author>
<published>2026-08-14T20:23:23Z</published>
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<entry>
<title>[CodeGen] Match LLVM Legalizer ownership</title>
<updated>2026-08-13T20:33:41Z</updated>
<author>
<name>Richard-Qin-X</name>
<email>richard.qin.001@gmail.com</email>
</author>
<published>2026-08-13T20:33:41Z</published>
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<id>urn:sha1:8be4d04455f70892a94d1e0798e266c948b4750a</id>
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</content>
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<entry>
<title>[CodeGen] Unify scalar low-level types</title>
<updated>2026-08-13T15:55:38Z</updated>
<author>
<name>Richard-Qin-X</name>
<email>richard.qin.001@gmail.com</email>
</author>
<published>2026-08-13T15:55:38Z</published>
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<id>urn:sha1:aa69e15c6909c3b162b15f5326f0a72ba9bb7163</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[CodeGen] Allow dynamic implicit operands on copies</title>
<updated>2026-08-11T19:36:43Z</updated>
<author>
<name>Richard-Qin-X</name>
<email>richard.qin.001@gmail.com</email>
</author>
<published>2026-08-11T19:36:43Z</published>
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<id>urn:sha1:165082bbec7097bc8385e10a2a6fcb6bdf7be75a</id>
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<entry>
<title>[CodeGen] Allow narrow atomic RMW memory types</title>
<updated>2026-08-11T18:44:40Z</updated>
<author>
<name>Richard-Qin-X</name>
<email>richard.qin.001@gmail.com</email>
</author>
<published>2026-08-11T18:44:40Z</published>
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<id>urn:sha1:23dad063b9172982467b69650ae334bbec63e759</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[RISCV] Legalize G_VAARG</title>
<updated>2026-08-11T18:14:52Z</updated>
<author>
<name>Richard-Qin-X</name>
<email>richard.qin.001@gmail.com</email>
</author>
<published>2026-08-11T18:14:52Z</published>
<link rel='alternate' type='text/html' href='https://git.richardqin.org/rcc-project/commit/?id=16b269164d072f3c0be713decc977c5c5f44f5e8'/>
<id>urn:sha1:16b269164d072f3c0be713decc977c5c5f44f5e8</id>
<content type='text'>
</content>
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<entry>
<title>[CodeGen] Accept pointer comparisons in G_ICMP</title>
<updated>2026-08-11T16:39:19Z</updated>
<author>
<name>Richard-Qin-X</name>
<email>richard.qin.001@gmail.com</email>
</author>
<published>2026-08-11T16:39:19Z</published>
<link rel='alternate' type='text/html' href='https://git.richardqin.org/rcc-project/commit/?id=524aad16ef496c849e812e972ed31b9d0db8c373'/>
<id>urn:sha1:524aad16ef496c849e812e972ed31b9d0db8c373</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[RISCV] Legalize narrow atomic compare exchange</title>
<updated>2026-08-11T09:59:16Z</updated>
<author>
<name>Richard-Qin-X</name>
<email>richard.qin.001@gmail.com</email>
</author>
<published>2026-08-11T09:59:16Z</published>
<link rel='alternate' type='text/html' href='https://git.richardqin.org/rcc-project/commit/?id=1e0003ec107dff77cd579d245f6314cbf7d4f3fc'/>
<id>urn:sha1:1e0003ec107dff77cd579d245f6314cbf7d4f3fc</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[RISCV] Legalize fixed-baseline RV64 MachineIR</title>
<updated>2026-08-11T09:38:11Z</updated>
<author>
<name>Richard-Qin-X</name>
<email>richard.qin.001@gmail.com</email>
</author>
<published>2026-08-11T09:38:11Z</published>
<link rel='alternate' type='text/html' href='https://git.richardqin.org/rcc-project/commit/?id=4fe5ee649927d54d6fb74904d7b97ad0f63fd587'/>
<id>urn:sha1:4fe5ee649927d54d6fb74904d7b97ad0f63fd587</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[CodeGen] Implement machine SSA exit</title>
<updated>2026-08-07T20:14:34Z</updated>
<author>
<name>Richard-Qin-X</name>
<email>richard.qin.001@gmail.com</email>
</author>
<published>2026-08-07T20:14:34Z</published>
<link rel='alternate' type='text/html' href='https://git.richardqin.org/rcc-project/commit/?id=77884c967d1cbc48afcbaef7e5a35adcb3c5da1b'/>
<id>urn:sha1:77884c967d1cbc48afcbaef7e5a35adcb3c5da1b</id>
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