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<title>rcc-project/backend/lib/CodeGen/GlobalISel/RegBankSelect.cpp, branch master</title>
<subtitle>An optimizing compiler for C.
</subtitle>
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<updated>2026-08-28T16:30:28Z</updated>
<entry>
<title>[GlobalISel] Bind register bank optionals once</title>
<updated>2026-08-28T16:30:28Z</updated>
<author>
<name>Richard-Qin-X</name>
<email>richard.qin.001@gmail.com</email>
</author>
<published>2026-08-28T16:30:28Z</published>
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<entry>
<title>[CodeGen] Centralize machine instruction erasure</title>
<updated>2026-08-28T05:45:07Z</updated>
<author>
<name>Richard-Qin-X</name>
<email>richard.qin.001@gmail.com</email>
</author>
<published>2026-08-28T05:45:07Z</published>
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<id>urn:sha1:e72ad2cd524ff38f162a23d69da5f78494d337ae</id>
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<entry>
<title>[CodeGen] Centralize machine pass property validation</title>
<updated>2026-08-26T15:28:39Z</updated>
<author>
<name>Richard-Qin-X</name>
<email>richard.qin.001@gmail.com</email>
</author>
<published>2026-08-26T15:28:39Z</published>
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<id>urn:sha1:a72a7a4323fb6eef8e15cc2f1229bcca14879e94</id>
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<entry>
<title>[RISCV][GlobalISel] Legalize floating-point remainder</title>
<updated>2026-08-15T12:03:59Z</updated>
<author>
<name>Richard-Qin-X</name>
<email>richard.qin.001@gmail.com</email>
</author>
<published>2026-08-15T12:03:59Z</published>
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<id>urn:sha1:5b6ba4568cf6916a61ecde702f45246db8154b9f</id>
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<entry>
<title>[RISCV] Match LLVM register bank mappings</title>
<updated>2026-08-13T11:04:49Z</updated>
<author>
<name>Richard-Qin-X</name>
<email>richard.qin.001@gmail.com</email>
</author>
<published>2026-08-13T11:04:49Z</published>
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<id>urn:sha1:1ef9d699d3160a9f79e89f423352fbb8d43e70d7</id>
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<entry>
<title>[Support] Centralize error context handling</title>
<updated>2026-08-13T05:18:05Z</updated>
<author>
<name>Richard-Qin-X</name>
<email>richard.qin.001@gmail.com</email>
</author>
<published>2026-08-13T05:18:05Z</published>
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<id>urn:sha1:8558f80b4077536d6aa46b97328d6df1210e261f</id>
<content type='text'>
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<entry>
<title>[CodeGen] Align pass manager ownership</title>
<updated>2026-08-12T21:45:37Z</updated>
<author>
<name>Richard-Qin-X</name>
<email>richard.qin.001@gmail.com</email>
</author>
<published>2026-08-12T21:45:37Z</published>
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<id>urn:sha1:236082a0fe4dcd0362c5c74923a93e3db6a01291</id>
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<entry>
<title>[CodeGen] Split machine liveness components</title>
<updated>2026-08-12T20:17:52Z</updated>
<author>
<name>Richard-Qin-X</name>
<email>richard.qin.001@gmail.com</email>
</author>
<published>2026-08-12T20:17:52Z</published>
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<id>urn:sha1:a2f8d7c5e22b510965327383410bd576f7cf28e7</id>
<content type='text'>
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<entry>
<title>[GlobalISel] Split the generic pipeline components</title>
<updated>2026-08-12T13:56:37Z</updated>
<author>
<name>Richard-Qin-X</name>
<email>richard.qin.001@gmail.com</email>
</author>
<published>2026-08-12T13:56:37Z</published>
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