rcc-project/backend/lib/CodeGen/InstructionDescriptor.cpp, branch masterAn optimizing compiler for C.
https://git.richardqin.org/rcc-project/atom?h=master2026-08-13T20:33:41Z[CodeGen] Match LLVM Legalizer ownership2026-08-13T20:33:41ZRichard-Qin-Xrichard.qin.001@gmail.com2026-08-13T20:33:41Zurn:sha1:8be4d04455f70892a94d1e0798e266c948b4750a[CodeGen] Unify scalar low-level types2026-08-13T15:55:38ZRichard-Qin-Xrichard.qin.001@gmail.com2026-08-13T15:55:38Zurn:sha1:aa69e15c6909c3b162b15f5326f0a72ba9bb7163[RISCV] Split the GlobalISel target components2026-08-12T14:37:49ZRichard-Qin-Xrichard.qin.001@gmail.com2026-08-12T14:37:49Zurn:sha1:3341938bb644e6fc39afa6a8fcb1306604999e42[MIR] Accept fixed-baseline LLVM syntax2026-08-11T09:37:42ZRichard-Qin-Xrichard.qin.001@gmail.com2026-08-11T09:37:42Zurn:sha1:6a7b083f322f4ac47e58cbf9d4d5fd4d1f6fecd0[CodeGen] Implement machine optimization and scheduling2026-08-09T09:03:19ZRichard-Qin-Xrichard.qin.001@gmail.com2026-08-09T09:03:19Zurn:sha1:495c675771f43cfa12ab7a426a538be72fec1805[CodeGen] Implement machine SSA exit2026-08-07T20:14:34ZRichard-Qin-Xrichard.qin.001@gmail.com2026-08-07T20:14:34Zurn:sha1:77884c967d1cbc48afcbaef7e5a35adcb3c5da1b[RISCV] Complete RV64GC instruction description2026-08-07T14:03:11ZRichard-Qin-Xrichard.qin.001@gmail.com2026-08-07T14:03:11Zurn:sha1:3e15bfd7b075209ec3b65d30d0611e060f6fbb77[CodeGen] Add target register descriptions2026-08-01T08:07:24ZRichard-Qin-Xrichard.qin.001@gmail.com2026-08-01T08:07:24Zurn:sha1:924dcd36ebed84f04729de05ec08b311a36a04c1
Introduce an immutable register topology for units, subregisters, classes, banks, and preserved masks. Bind instruction descriptors to this topology through TargetDescription so builders, cloning, and verification share one target-aware contract. Add the test-only TestTarget model and positive and negative target fact coverage.
[CodeGen] Add transactional MachineIR builder2026-08-01T05:09:30ZRichard-Qin-Xrichard.qin.001@gmail.com2026-08-01T05:09:30Zurn:sha1:8553df97bbc6154dae9d0ad861857e71a0efa420
Validate insertion cursors, operand ownership, descriptor constraints, ties, implicit registers, and memory operands before allocating or publishing an instruction. Share instruction legality checks with the verifier path and preserve deterministic insertion order.
[CodeGen] Add machine instruction descriptors2026-08-01T04:05:36ZRichard-Qin-Xrichard.qin.001@gmail.com2026-08-01T04:05:36Zurn:sha1:fd8770b01a7a3ae85ba85fb43b21803c88593ad7
Introduce an immutable instruction registry with exact operand, implicit register, tie, pseudo lifecycle, and memory constraints. Validate descriptor tables before publication and use the same rules to verify MachineInstr instances.