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<title>rcc-project/backend/lib/CodeGen/MIRPrinter.cpp, branch master</title>
<subtitle>An optimizing compiler for C.
</subtitle>
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<updated>2026-08-25T16:50:21Z</updated>
<entry>
<title>[CodeGen] Implement reaching-def analysis printing</title>
<updated>2026-08-25T16:50:21Z</updated>
<author>
<name>Richard-Qin-X</name>
<email>richard.qin.001@gmail.com</email>
</author>
<published>2026-08-25T16:50:21Z</published>
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<id>urn:sha1:d54646c69a5117cbeef35f5c3f0d546f4c6bf0e7</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[CodeGen] Implement the greedy register allocator pipeline</title>
<updated>2026-08-24T19:11:23Z</updated>
<author>
<name>Richard-Qin-X</name>
<email>richard.qin.001@gmail.com</email>
</author>
<published>2026-08-24T19:11:23Z</published>
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<id>urn:sha1:f5d9ddc085055d28d6f9fb3730c3566097f43fb2</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[RISCV] Match LLVM large call frame lowering</title>
<updated>2026-08-24T10:13:23Z</updated>
<author>
<name>Richard-Qin-X</name>
<email>richard.qin.001@gmail.com</email>
</author>
<published>2026-08-24T10:13:23Z</published>
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<id>urn:sha1:1b4601c1ac91a06091610e969e70bcd1cb014cc5</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[RISCV] Match LLVM frame lowering semantics</title>
<updated>2026-08-24T08:37:25Z</updated>
<author>
<name>Richard-Qin-X</name>
<email>richard.qin.001@gmail.com</email>
</author>
<published>2026-08-24T08:37:25Z</published>
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<id>urn:sha1:540c73a2f450af3d0aec6e039fab054471efdbb1</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[CodeGen] Match LLVM machine debug stripping</title>
<updated>2026-08-22T10:59:22Z</updated>
<author>
<name>Richard-Qin-X</name>
<email>richard.qin.001@gmail.com</email>
</author>
<published>2026-08-22T10:59:22Z</published>
<link rel='alternate' type='text/html' href='https://git.richardqin.org/rcc-project/commit/?id=36b0be1ec1558f88d4f031a1817c3a4c2cba07a6'/>
<id>urn:sha1:36b0be1ec1558f88d4f031a1817c3a4c2cba07a6</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[MIR] Print target generic operand types</title>
<updated>2026-08-14T17:34:21Z</updated>
<author>
<name>Richard-Qin-X</name>
<email>richard.qin.001@gmail.com</email>
</author>
<published>2026-08-14T17:34:21Z</published>
<link rel='alternate' type='text/html' href='https://git.richardqin.org/rcc-project/commit/?id=c8bad4713f17c3624a6044885ee43d316953b598'/>
<id>urn:sha1:c8bad4713f17c3624a6044885ee43d316953b598</id>
<content type='text'>
Use the instruction descriptor's Generic flag when deduplicating LLT annotations so target-specific generic pseudos follow LLVM MIR spelling.
</content>
</entry>
<entry>
<title>[CodeGen] Unify scalar low-level types</title>
<updated>2026-08-13T15:55:38Z</updated>
<author>
<name>Richard-Qin-X</name>
<email>richard.qin.001@gmail.com</email>
</author>
<published>2026-08-13T15:55:38Z</published>
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<id>urn:sha1:aa69e15c6909c3b162b15f5326f0a72ba9bb7163</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[MIR] Omit predictable successors in simplified output</title>
<updated>2026-08-13T11:03:08Z</updated>
<author>
<name>Richard-Qin-X</name>
<email>richard.qin.001@gmail.com</email>
</author>
<published>2026-08-13T11:03:08Z</published>
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<id>urn:sha1:1ecaa5028a39cdfd9b9590053d802e8049d346d5</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[CodeGen] Preserve LLT annotations on generic opcodes</title>
<updated>2026-08-13T10:52:39Z</updated>
<author>
<name>Richard-Qin-X</name>
<email>richard.qin.001@gmail.com</email>
</author>
<published>2026-08-13T10:52:39Z</published>
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<id>urn:sha1:5794302adc3ce94c69318965b1bbef7a895d5d41</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[IR] Split LL parsing, assembly writing, and data layout</title>
<updated>2026-08-13T04:55:12Z</updated>
<author>
<name>Richard-Qin-X</name>
<email>richard.qin.001@gmail.com</email>
</author>
<published>2026-08-13T04:55:12Z</published>
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<id>urn:sha1:fde3e045d4dcc5c404cb4216389e18b0e720b8e0</id>
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</content>
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