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<title>rcc-project/backend/lib/CodeGen/MachineCFGUpdater.cpp, branch master</title>
<subtitle>An optimizing compiler for C.
</subtitle>
<id>https://git.richardqin.org/rcc-project/atom?h=master</id>
<link rel='self' href='https://git.richardqin.org/rcc-project/atom?h=master'/>
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<updated>2026-08-28T05:45:07Z</updated>
<entry>
<title>[CodeGen] Centralize machine instruction erasure</title>
<updated>2026-08-28T05:45:07Z</updated>
<author>
<name>Richard-Qin-X</name>
<email>richard.qin.001@gmail.com</email>
</author>
<published>2026-08-28T05:45:07Z</published>
<link rel='alternate' type='text/html' href='https://git.richardqin.org/rcc-project/commit/?id=e72ad2cd524ff38f162a23d69da5f78494d337ae'/>
<id>urn:sha1:e72ad2cd524ff38f162a23d69da5f78494d337ae</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[CodeGen] Implement machine SSA exit</title>
<updated>2026-08-07T20:14:34Z</updated>
<author>
<name>Richard-Qin-X</name>
<email>richard.qin.001@gmail.com</email>
</author>
<published>2026-08-07T20:14:34Z</published>
<link rel='alternate' type='text/html' href='https://git.richardqin.org/rcc-project/commit/?id=77884c967d1cbc48afcbaef7e5a35adcb3c5da1b'/>
<id>urn:sha1:77884c967d1cbc48afcbaef7e5a35adcb3c5da1b</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[CodeGen] Build the core MachineIR object model</title>
<updated>2026-07-31T21:27:13Z</updated>
<author>
<name>Richard-Qin-X</name>
<email>richard.qin.001@gmail.com</email>
</author>
<published>2026-07-31T21:27:13Z</published>
<link rel='alternate' type='text/html' href='https://git.richardqin.org/rcc-project/commit/?id=c759cebef15bdac2ef160065efd116fe6ed540a7'/>
<id>urn:sha1:c759cebef15bdac2ef160065efd116fe6ed540a7</id>
<content type='text'>
Add arena-owned, address-stable MachineFunction, MachineBasicBlock, and MachineInstr nodes with intrusive layout and instruction lists. Model every required MachineOperand category, reciprocal ties, source state, and immutable per-instruction memory references.

Implement physical and virtual register def-use chains whose back-links survive operand vector moves, plus vreg properties, tombstones, live-ins, reserved registers, and atomic CFG updates. Exercise ownership, reallocation, unlink/relink, cross-function rejection, and sanitizer paths.
</content>
</entry>
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