rcc-project/backend/lib/CodeGen/MachineFunction.cpp, branch masterAn optimizing compiler for C.
https://git.richardqin.org/rcc-project/atom?h=master2026-08-11T09:37:42Z[MIR] Accept fixed-baseline LLVM syntax2026-08-11T09:37:42ZRichard-Qin-Xrichard.qin.001@gmail.com2026-08-11T09:37:42Zurn:sha1:6a7b083f322f4ac47e58cbf9d4d5fd4d1f6fecd0[CodeGen] Implement machine optimization and scheduling2026-08-09T09:03:19ZRichard-Qin-Xrichard.qin.001@gmail.com2026-08-09T09:03:19Zurn:sha1:495c675771f43cfa12ab7a426a538be72fec1805[CodeGen] Track debug instruction identities2026-08-01T10:17:33ZRichard-Qin-Xrichard.qin.001@gmail.com2026-08-01T10:17:33Zurn:sha1:e0c77d80585428818c32886eb8c26755ea8ed159
Add monotonic MIR debug instruction numbers and structured value substitutions. Verify live number uniqueness, meta-instruction exclusion, substitution graph integrity, and target subregister references while preserving debug identities during cloning.
[CodeGen] Add target state and compilation status2026-08-01T06:50:04ZRichard-Qin-Xrichard.qin.001@gmail.com2026-08-01T06:50:04Zurn:sha1:cfdbcc469f9691bd9dce3b0b86982a63d86ca6b7[CodeGen] Add constant and jump table state2026-08-01T06:19:20ZRichard-Qin-Xrichard.qin.001@gmail.com2026-08-01T06:19:20Zurn:sha1:a69d14b8ebc028dddc689658b08d42d3e83f5e38
Add stable, tombstone-preserving MachineConstantPool and MachineJumpTableInfo ownership. Define the versioned TargetConstant contract and integrate all table references with builders, verification, and deterministic deep cloning.
[CMake] Match LLVM EH and RTTI defaults2026-08-01T05:01:07ZRichard-Qin-Xrichard.qin.001@gmail.com2026-08-01T05:01:07Zurn:sha1:b4d1ddb99e1305f6ea6217e7570dda2a94b16e51
Disable C++ exceptions and RTTI by default while retaining explicit, validated opt-in switches. Replace the arena's exception syntax with an RAII construction guard so both configurations share one implementation.
[CodeGen] Build the core MachineIR object model2026-07-31T21:27:13ZRichard-Qin-Xrichard.qin.001@gmail.com2026-07-31T21:27:13Zurn:sha1:c759cebef15bdac2ef160065efd116fe6ed540a7
Add arena-owned, address-stable MachineFunction, MachineBasicBlock, and MachineInstr nodes with intrusive layout and instruction lists. Model every required MachineOperand category, reciprocal ties, source state, and immutable per-instruction memory references.
Implement physical and virtual register def-use chains whose back-links survive operand vector moves, plus vreg properties, tombstones, live-ins, reserved registers, and atomic CFG updates. Exercise ownership, reallocation, unlink/relink, cross-function rejection, and sanitizer paths.