<feed xmlns='http://www.w3.org/2005/Atom'>
<title>rcc-project/backend/lib/CodeGen/MachineFunctionCloner.cpp, branch master</title>
<subtitle>An optimizing compiler for C.
</subtitle>
<id>https://git.richardqin.org/rcc-project/atom?h=master</id>
<link rel='self' href='https://git.richardqin.org/rcc-project/atom?h=master'/>
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<updated>2026-08-12T14:37:49Z</updated>
<entry>
<title>[RISCV] Split the GlobalISel target components</title>
<updated>2026-08-12T14:37:49Z</updated>
<author>
<name>Richard-Qin-X</name>
<email>richard.qin.001@gmail.com</email>
</author>
<published>2026-08-12T14:37:49Z</published>
<link rel='alternate' type='text/html' href='https://git.richardqin.org/rcc-project/commit/?id=3341938bb644e6fc39afa6a8fcb1306604999e42'/>
<id>urn:sha1:3341938bb644e6fc39afa6a8fcb1306604999e42</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[MIR] Accept fixed-baseline LLVM syntax</title>
<updated>2026-08-11T09:37:42Z</updated>
<author>
<name>Richard-Qin-X</name>
<email>richard.qin.001@gmail.com</email>
</author>
<published>2026-08-11T09:37:42Z</published>
<link rel='alternate' type='text/html' href='https://git.richardqin.org/rcc-project/commit/?id=6a7b083f322f4ac47e58cbf9d4d5fd4d1f6fecd0'/>
<id>urn:sha1:6a7b083f322f4ac47e58cbf9d4d5fd4d1f6fecd0</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[CodeGen] Complete register allocation infrastructure</title>
<updated>2026-08-08T20:40:17Z</updated>
<author>
<name>Richard-Qin-X</name>
<email>richard.qin.001@gmail.com</email>
</author>
<published>2026-08-08T20:40:17Z</published>
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<id>urn:sha1:e5fdceb9b869f010a2a75638fd38aaf1867f3008</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[MIR] Complete document parsing and printing</title>
<updated>2026-08-06T17:27:41Z</updated>
<author>
<name>Richard-Qin-X</name>
<email>richard.qin.001@gmail.com</email>
</author>
<published>2026-08-06T17:27:41Z</published>
<link rel='alternate' type='text/html' href='https://git.richardqin.org/rcc-project/commit/?id=76d89700953ddd81cf31ab8f260eddf67e93aa85'/>
<id>urn:sha1:76d89700953ddd81cf31ab8f260eddf67e93aa85</id>
<content type='text'>
Implement the single LLVM-compatible MIR document path with structured\nembedded-IR references, YAML mappings, constants, and deterministic printing.\n\nKeep pointer LLT widths DataLayout-derived, reject layout-dependent output\nwhen embedded IR is omitted, and record the fixed-baseline compatibility\ncontract and regression coverage.
</content>
</entry>
<entry>
<title>[MIR] Add machine instruction parser and printer</title>
<updated>2026-08-03T21:34:15Z</updated>
<author>
<name>Richard-Qin-X</name>
<email>richard.qin.001@gmail.com</email>
</author>
<published>2026-08-03T21:34:15Z</published>
<link rel='alternate' type='text/html' href='https://git.richardqin.org/rcc-project/commit/?id=183e2354e9fdd107be420cbb185c1d239434aa48'/>
<id>urn:sha1:183e2354e9fdd107be420cbb185c1d239434aa48</id>
<content type='text'>
Parse MachineFunction bodies in two passes and serialize the same MachineIR model in complete or readable form. Extend instruction attachments and memory operands required by the fixed LLVM MIR grammar, and cover deterministic parse-print round trips.
</content>
</entry>
<entry>
<title>[CodeGen] Add target MIR text schema</title>
<updated>2026-08-03T11:24:30Z</updated>
<author>
<name>Richard-Qin-X</name>
<email>richard.qin.001@gmail.com</email>
</author>
<published>2026-08-03T11:24:30Z</published>
<link rel='alternate' type='text/html' href='https://git.richardqin.org/rcc-project/commit/?id=432efe39315ed5ad0162f9c08dbf10941bc21dc1'/>
<id>urn:sha1:432efe39315ed5ad0162f9c08dbf10941bc21dc1</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[CodeGen] Model complete MIR operands</title>
<updated>2026-08-03T10:31:58Z</updated>
<author>
<name>Richard-Qin-X</name>
<email>richard.qin.001@gmail.com</email>
</author>
<published>2026-08-03T10:31:58Z</published>
<link rel='alternate' type='text/html' href='https://git.richardqin.org/rcc-project/commit/?id=6580ac1c05bd1cbccd2dcd71fd9c2a384ae3db56'/>
<id>urn:sha1:6580ac1c05bd1cbccd2dcd71fd9c2a384ae3db56</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[CodeGen] Model machine debug metadata</title>
<updated>2026-08-01T19:37:46Z</updated>
<author>
<name>Richard-Qin-X</name>
<email>richard.qin.001@gmail.com</email>
</author>
<published>2026-08-01T19:37:46Z</published>
<link rel='alternate' type='text/html' href='https://git.richardqin.org/rcc-project/commit/?id=a8a9d7d926202450645deae872d4d9dc11d63215'/>
<id>urn:sha1:a8a9d7d926202450645deae872d4d9dc11d63215</id>
<content type='text'>
Replace marker-based metadata operands with scoped references and inline DIExpression values. Add structured DILocation chains, instruction debug attachments, stack variable records, and entry values with unified verification, builder support, and deterministic cloning.
</content>
</entry>
<entry>
<title>[CodeGen] Add machine metadata graphs</title>
<updated>2026-08-01T18:56:39Z</updated>
<author>
<name>Richard-Qin-X</name>
<email>richard.qin.001@gmail.com</email>
</author>
<published>2026-08-01T18:56:39Z</published>
<link rel='alternate' type='text/html' href='https://git.richardqin.org/rcc-project/commit/?id=49d70380a6a95e4039f6b5e5ccce09671d5b4796'/>
<id>urn:sha1:49d70380a6a95e4039f6b5e5ccce09671d5b4796</id>
<content type='text'>
Model ordered function-local metadata tuples with explicit embedded-IR and MachineFunction reference scopes. Preserve slot zero, distinct nodes, forward references, and cyclic graphs while verifying function-local closure and cloning the graph deterministically.
</content>
</entry>
<entry>
<title>[CodeGen] Track debug instruction identities</title>
<updated>2026-08-01T10:17:33Z</updated>
<author>
<name>Richard-Qin-X</name>
<email>richard.qin.001@gmail.com</email>
</author>
<published>2026-08-01T10:17:33Z</published>
<link rel='alternate' type='text/html' href='https://git.richardqin.org/rcc-project/commit/?id=e0c77d80585428818c32886eb8c26755ea8ed159'/>
<id>urn:sha1:e0c77d80585428818c32886eb8c26755ea8ed159</id>
<content type='text'>
Add monotonic MIR debug instruction numbers and structured value substitutions. Verify live number uniqueness, meta-instruction exclusion, substitution graph integrity, and target subregister references while preserving debug identities during cloning.
</content>
</entry>
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