<feed xmlns='http://www.w3.org/2005/Atom'>
<title>rcc-project/backend/lib/CodeGen/PostRAScheduler.cpp, branch master</title>
<subtitle>An optimizing compiler for C.
</subtitle>
<id>https://git.richardqin.org/rcc-project/atom?h=master</id>
<link rel='self' href='https://git.richardqin.org/rcc-project/atom?h=master'/>
<link rel='alternate' type='text/html' href='https://git.richardqin.org/rcc-project/'/>
<updated>2026-08-26T15:48:41Z</updated>
<entry>
<title>[CodeGen] Run scheduling transformations once</title>
<updated>2026-08-26T15:48:41Z</updated>
<author>
<name>Richard-Qin-X</name>
<email>richard.qin.001@gmail.com</email>
</author>
<published>2026-08-26T15:48:41Z</published>
<link rel='alternate' type='text/html' href='https://git.richardqin.org/rcc-project/commit/?id=a932de71457e16030d7d05e4230c56e231c7a8e9'/>
<id>urn:sha1:a932de71457e16030d7d05e4230c56e231c7a8e9</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[CodeGen] Generate RISC-V macro fusion rules</title>
<updated>2026-08-22T10:49:08Z</updated>
<author>
<name>Richard-Qin-X</name>
<email>richard.qin.001@gmail.com</email>
</author>
<published>2026-08-22T10:49:08Z</published>
<link rel='alternate' type='text/html' href='https://git.richardqin.org/rcc-project/commit/?id=8a4bb6e3b0bffa0ed79b51347b12ee4293b622a7'/>
<id>urn:sha1:8a4bb6e3b0bffa0ed79b51347b12ee4293b622a7</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[CodeGen] Match LLVM post-machine scheduler contract</title>
<updated>2026-08-19T09:34:09Z</updated>
<author>
<name>Richard-Qin-X</name>
<email>richard.qin.001@gmail.com</email>
</author>
<published>2026-08-19T09:34:09Z</published>
<link rel='alternate' type='text/html' href='https://git.richardqin.org/rcc-project/commit/?id=b1e89e3948dba01baf86e3518c6bdd3efff08ce5'/>
<id>urn:sha1:b1e89e3948dba01baf86e3518c6bdd3efff08ce5</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[Support] Centralize error context handling</title>
<updated>2026-08-13T05:18:05Z</updated>
<author>
<name>Richard-Qin-X</name>
<email>richard.qin.001@gmail.com</email>
</author>
<published>2026-08-13T05:18:05Z</published>
<link rel='alternate' type='text/html' href='https://git.richardqin.org/rcc-project/commit/?id=8558f80b4077536d6aa46b97328d6df1210e261f'/>
<id>urn:sha1:8558f80b4077536d6aa46b97328d6df1210e261f</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[CodeGen] Align pass manager ownership</title>
<updated>2026-08-12T21:45:37Z</updated>
<author>
<name>Richard-Qin-X</name>
<email>richard.qin.001@gmail.com</email>
</author>
<published>2026-08-12T21:45:37Z</published>
<link rel='alternate' type='text/html' href='https://git.richardqin.org/rcc-project/commit/?id=236082a0fe4dcd0362c5c74923a93e3db6a01291'/>
<id>urn:sha1:236082a0fe4dcd0362c5c74923a93e3db6a01291</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[CodeGen] Split machine liveness components</title>
<updated>2026-08-12T20:17:52Z</updated>
<author>
<name>Richard-Qin-X</name>
<email>richard.qin.001@gmail.com</email>
</author>
<published>2026-08-12T20:17:52Z</published>
<link rel='alternate' type='text/html' href='https://git.richardqin.org/rcc-project/commit/?id=a2f8d7c5e22b510965327383410bd576f7cf28e7'/>
<id>urn:sha1:a2f8d7c5e22b510965327383410bd576f7cf28e7</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[Tooling] Complete the LLVM MIR command-line contract</title>
<updated>2026-08-12T11:45:09Z</updated>
<author>
<name>Richard-Qin-X</name>
<email>richard.qin.001@gmail.com</email>
</author>
<published>2026-08-12T11:45:09Z</published>
<link rel='alternate' type='text/html' href='https://git.richardqin.org/rcc-project/commit/?id=09e8ef3e0dae29be7aa21a6e22a118a3f545945f'/>
<id>urn:sha1:09e8ef3e0dae29be7aa21a6e22a118a3f545945f</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[CodeGen] Track reserved register defs precisely</title>
<updated>2026-08-11T17:22:08Z</updated>
<author>
<name>Richard-Qin-X</name>
<email>richard.qin.001@gmail.com</email>
</author>
<published>2026-08-11T17:22:08Z</published>
<link rel='alternate' type='text/html' href='https://git.richardqin.org/rcc-project/commit/?id=0e43f63ac7fa5e28497760a0dfec2fe20557bce0'/>
<id>urn:sha1:0e43f63ac7fa5e28497760a0dfec2fe20557bce0</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[RISCV] Model FFLAGS accesses</title>
<updated>2026-08-11T17:07:48Z</updated>
<author>
<name>Richard-Qin-X</name>
<email>richard.qin.001@gmail.com</email>
</author>
<published>2026-08-11T17:07:48Z</published>
<link rel='alternate' type='text/html' href='https://git.richardqin.org/rcc-project/commit/?id=7819df7189a54fa5b8df657d10285f1873628d25'/>
<id>urn:sha1:7819df7189a54fa5b8df657d10285f1873628d25</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[Tooling] Complete backend tooling and validation</title>
<updated>2026-08-10T12:36:50Z</updated>
<author>
<name>Richard-Qin-X</name>
<email>richard.qin.001@gmail.com</email>
</author>
<published>2026-08-10T12:36:50Z</published>
<link rel='alternate' type='text/html' href='https://git.richardqin.org/rcc-project/commit/?id=adcf8c9b1bd1b47e00bf859693112cea1f7e8c9f'/>
<id>urn:sha1:adcf8c9b1bd1b47e00bf859693112cea1f7e8c9f</id>
<content type='text'>
</content>
</entry>
</feed>
