rcc-project/backend/lib/CodeGen/TargetDescription.cpp, branch master An optimizing compiler for C. https://git.richardqin.org/rcc-project/atom?h=master 2026-08-22T10:49:08Z [CodeGen] Generate RISC-V macro fusion rules 2026-08-22T10:49:08Z Richard-Qin-X richard.qin.001@gmail.com 2026-08-22T10:49:08Z urn:sha1:8a4bb6e3b0bffa0ed79b51347b12ee4293b622a7 [RISCV][GlobalISel] Generate integer comparisons 2026-08-16T09:28:49Z Richard-Qin-X richard.qin.001@gmail.com 2026-08-16T09:28:49Z urn:sha1:864a29abbdce86353ec91c3587757711d3a42f10 [GlobalISel] Lower stack operations 2026-08-14T20:48:16Z Richard-Qin-X richard.qin.001@gmail.com 2026-08-14T20:48:16Z urn:sha1:32a365a2dc0096b4421fb3947b32d971b7f34c40 [GlobalISel] Match LLVM legalization value tracking 2026-08-14T12:35:54Z Richard-Qin-X richard.qin.001@gmail.com 2026-08-14T12:35:54Z urn:sha1:97e5fbaa55b4672db36123c2425d05a4738452ab [CodeGen] Unify scalar low-level types 2026-08-13T15:55:38Z Richard-Qin-X richard.qin.001@gmail.com 2026-08-13T15:55:38Z urn:sha1:aa69e15c6909c3b162b15f5326f0a72ba9bb7163 [CodeGen] Implement machine SSA exit 2026-08-07T20:14:34Z Richard-Qin-X richard.qin.001@gmail.com 2026-08-07T20:14:34Z urn:sha1:77884c967d1cbc48afcbaef7e5a35adcb3c5da1b [RISCV] Add generated RV64GC register description 2026-08-06T18:15:09Z Richard-Qin-X richard.qin.001@gmail.com 2026-08-06T18:15:09Z urn:sha1:e16de95dce32f077361577377d5c52fc4ad78339 Add an RCC-owned build-time target description generator and the initial RV64GC register model. Keep ABI aliases separate from canonical MIR register spelling. [CodeGen] Add target MIR text schema 2026-08-03T11:24:30Z Richard-Qin-X richard.qin.001@gmail.com 2026-08-03T11:24:30Z urn:sha1:432efe39315ed5ad0162f9c08dbf10941bc21dc1 [CodeGen] Model complete MIR operands 2026-08-03T10:31:58Z Richard-Qin-X richard.qin.001@gmail.com 2026-08-03T10:31:58Z urn:sha1:6580ac1c05bd1cbccd2dcd71fd9c2a384ae3db56 [CodeGen] Add target register descriptions 2026-08-01T08:07:24Z Richard-Qin-X richard.qin.001@gmail.com 2026-08-01T08:07:24Z urn:sha1:924dcd36ebed84f04729de05ec08b311a36a04c1 Introduce an immutable register topology for units, subregisters, classes, banks, and preserved masks. Bind instruction descriptors to this topology through TargetDescription so builders, cloning, and verification share one target-aware contract. Add the test-only TestTarget model and positive and negative target fact coverage.