rcc-project/backend/lib/Target/Description/TargetDescriptionGenerator.cpp, branch master

rcc-project/backend/lib/Target/Description/TargetDescriptionGenerator.cpp, branch master An optimizing compiler for C. https://git.richardqin.org/rcc-project/atom?h=master 2026-08-13T05:10:47Z [TableGen] Split the target description generator 2026-08-13T05:10:47Z Richard-Qin-X richard.qin.001@gmail.com 2026-08-13T05:10:47Z urn:sha1:444db30751380e8fe459bfeae4c5bb2a93c596eb [RISCV] Model typed floating-point register views 2026-08-11T15:44:57Z Richard-Qin-X richard.qin.001@gmail.com 2026-08-11T15:44:57Z urn:sha1:e6cd1347cc2c76babe56842e1b7bd05d68fe9584 [MC] Implement RV64GC object emission 2026-08-09T14:05:14Z Richard-Qin-X richard.qin.001@gmail.com 2026-08-09T14:05:14Z urn:sha1:3a57627e59ba18b6f9f9aae7bb60c390c0d3575a [CodeGen] Implement machine optimization and scheduling 2026-08-09T09:03:19Z Richard-Qin-X richard.qin.001@gmail.com 2026-08-09T09:03:19Z urn:sha1:495c675771f43cfa12ab7a426a538be72fec1805 [CodeGen] Complete register allocation infrastructure 2026-08-08T20:40:17Z Richard-Qin-X richard.qin.001@gmail.com 2026-08-08T20:40:17Z urn:sha1:e5fdceb9b869f010a2a75638fd38aaf1867f3008 [RISCV] Complete RV64GC instruction description 2026-08-07T14:03:11Z Richard-Qin-X richard.qin.001@gmail.com 2026-08-07T14:03:11Z urn:sha1:3e15bfd7b075209ec3b65d30d0611e060f6fbb77 [RISCV] Add generated RV64GC register description 2026-08-06T18:15:09Z Richard-Qin-X richard.qin.001@gmail.com 2026-08-06T18:15:09Z urn:sha1:e16de95dce32f077361577377d5c52fc4ad78339 Add an RCC-owned build-time target description generator and the initial RV64GC register model. Keep ABI aliases separate from canonical MIR register spelling.