rcc-project/backend/lib/Target/RISCV/GISel, branch master

rcc-project/backend/lib/Target/RISCV/GISel, branch master An optimizing compiler for C. https://git.richardqin.org/rcc-project/atom?h=master 2026-08-28T16:41:28Z [RISCV] Merge identical selector cases 2026-08-28T16:41:28Z Richard-Qin-X richard.qin.001@gmail.com 2026-08-28T16:41:28Z urn:sha1:1481dd5b62a8a914e593206d72e1aff99ced2af4 [RISCV] Widen jump table entry size arithmetic 2026-08-28T16:38:11Z Richard-Qin-X richard.qin.001@gmail.com 2026-08-28T16:38:11Z urn:sha1:6b07676fa9177bbf971afaf898dd9997e0664b95 [CodeGen] Apply LLVM declaration style 2026-08-28T16:24:17Z Richard-Qin-X richard.qin.001@gmail.com 2026-08-28T16:24:17Z urn:sha1:36b5b862c8ab2f75606e23466a3c758ff6d9358b [RISCV] Separate calling convention assignment 2026-08-28T06:07:11Z Richard-Qin-X richard.qin.001@gmail.com 2026-08-28T06:07:11Z urn:sha1:6e8feb15a0d256ca19e88185f78c81f689ce7d34 [CodeGen] Centralize machine instruction erasure 2026-08-28T05:45:07Z Richard-Qin-X richard.qin.001@gmail.com 2026-08-28T05:45:07Z urn:sha1:e72ad2cd524ff38f162a23d69da5f78494d337ae [GlobalISel] Generate floating memory selection 2026-08-27T09:13:36Z Richard-Qin-X richard.qin.001@gmail.com 2026-08-27T09:13:36Z urn:sha1:3b14bd4d5324b5a280c1ee5567b5526b59e60c5b [RISCV] Generate atomic RMW selection 2026-08-27T08:27:25Z Richard-Qin-X richard.qin.001@gmail.com 2026-08-27T08:27:25Z urn:sha1:dd477bc887546b00144ea6c0a3e03ad366661636 [RISCV] Remove unused selector helpers 2026-08-27T08:13:48Z Richard-Qin-X richard.qin.001@gmail.com 2026-08-27T08:13:48Z urn:sha1:c342b791ba415f2eb763a6548abd4c469641a549 [GlobalISel] Select each instruction once 2026-08-27T08:09:44Z Richard-Qin-X richard.qin.001@gmail.com 2026-08-27T08:09:44Z urn:sha1:12dcc180caf1f1e416456277f2dcb92fbe260c3d [CodeGen] Generate RISC-V macro fusion rules 2026-08-22T10:49:08Z Richard-Qin-X richard.qin.001@gmail.com 2026-08-22T10:49:08Z urn:sha1:8a4bb6e3b0bffa0ed79b51347b12ee4293b622a7