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<title>rcc-project/backend/lib/Target/RISCV/RISCVInstPrinter.cpp, branch master</title>
<subtitle>An optimizing compiler for C.
</subtitle>
<id>https://git.richardqin.org/rcc-project/atom?h=master</id>
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<updated>2026-08-28T11:15:07Z</updated>
<entry>
<title>[RISCV] Generate complete Zcmp instruction definitions</title>
<updated>2026-08-28T11:15:07Z</updated>
<author>
<name>Richard-Qin-X</name>
<email>richard.qin.001@gmail.com</email>
</author>
<published>2026-08-28T11:15:07Z</published>
<link rel='alternate' type='text/html' href='https://git.richardqin.org/rcc-project/commit/?id=b1c08d57f1637f5ee813d1409dacdfa88c1509a0'/>
<id>urn:sha1:b1c08d57f1637f5ee813d1409dacdfa88c1509a0</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[RISCV][GlobalISel] Select and expand global addresses</title>
<updated>2026-08-18T20:27:41Z</updated>
<author>
<name>Richard-Qin-X</name>
<email>richard.qin.001@gmail.com</email>
</author>
<published>2026-08-18T20:27:41Z</published>
<link rel='alternate' type='text/html' href='https://git.richardqin.org/rcc-project/commit/?id=307fc0961972ac5264d6f3459978fbec95cad3a9'/>
<id>urn:sha1:307fc0961972ac5264d6f3459978fbec95cad3a9</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[RISCV] Add Zba and Zbb instruction descriptions</title>
<updated>2026-08-11T19:02:45Z</updated>
<author>
<name>Richard-Qin-X</name>
<email>richard.qin.001@gmail.com</email>
</author>
<published>2026-08-11T19:02:45Z</published>
<link rel='alternate' type='text/html' href='https://git.richardqin.org/rcc-project/commit/?id=888e9b5bb57a79f4eee88a7926cb859e04823361'/>
<id>urn:sha1:888e9b5bb57a79f4eee88a7926cb859e04823361</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[RISCV] Support absolute address operand flags</title>
<updated>2026-08-11T16:26:10Z</updated>
<author>
<name>Richard-Qin-X</name>
<email>richard.qin.001@gmail.com</email>
</author>
<published>2026-08-11T16:26:10Z</published>
<link rel='alternate' type='text/html' href='https://git.richardqin.org/rcc-project/commit/?id=d91d57297bdb30b6363e259ab75d517dc333e292'/>
<id>urn:sha1:d91d57297bdb30b6363e259ab75d517dc333e292</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[RISCV] Model typed floating-point register views</title>
<updated>2026-08-11T15:44:57Z</updated>
<author>
<name>Richard-Qin-X</name>
<email>richard.qin.001@gmail.com</email>
</author>
<published>2026-08-11T15:44:57Z</published>
<link rel='alternate' type='text/html' href='https://git.richardqin.org/rcc-project/commit/?id=e6cd1347cc2c76babe56842e1b7bd05d68fe9584'/>
<id>urn:sha1:e6cd1347cc2c76babe56842e1b7bd05d68fe9584</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[MC] Implement RV64GC assembly emission</title>
<updated>2026-08-09T10:31:49Z</updated>
<author>
<name>Richard-Qin-X</name>
<email>richard.qin.001@gmail.com</email>
</author>
<published>2026-08-09T10:31:49Z</published>
<link rel='alternate' type='text/html' href='https://git.richardqin.org/rcc-project/commit/?id=379ff50dcc7ccf977379aee68fa9d10f69065d23'/>
<id>urn:sha1:379ff50dcc7ccf977379aee68fa9d10f69065d23</id>
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