rcc-project/backend/lib/Target/RISCV/RISCVInstrInfo.cpp, branch master
An optimizing compiler for C.
https://git.richardqin.org/rcc-project/atom?h=master
2026-08-28T05:45:07Z
[CodeGen] Centralize machine instruction erasure
2026-08-28T05:45:07Z
Richard-Qin-X
richard.qin.001@gmail.com
2026-08-28T05:45:07Z
urn:sha1:e72ad2cd524ff38f162a23d69da5f78494d337ae
[CodeGen] Implement RISC-V peephole branch optimization
2026-08-24T08:18:45Z
Richard-Qin-X
richard.qin.001@gmail.com
2026-08-24T08:18:45Z
urn:sha1:936ac5647f82def050e6654d44d24a88906f4d7a
[CodeGen] Match LLVM machine copy propagation
2026-08-13T13:11:10Z
Richard-Qin-X
richard.qin.001@gmail.com
2026-08-13T13:11:10Z
urn:sha1:cd30fb546e389d1fb78ce8e579b3dba3a8fdb52a
[CodeGen] Match LLVM branch relaxation semantics
2026-08-13T11:38:37Z
Richard-Qin-X
richard.qin.001@gmail.com
2026-08-13T11:38:37Z
urn:sha1:98cae0e8835a1eb8fcb0e43870c04ed934cc51ac
[RISCV] Remove physical register forwarding helpers
2026-08-13T05:23:58Z
Richard-Qin-X
richard.qin.001@gmail.com
2026-08-13T05:23:58Z
urn:sha1:393e95fb39d1ddb366b1f17a51166cb3612bbbbd
[RISCV] Use the generated opcode conversion
2026-08-13T05:21:44Z
Richard-Qin-X
richard.qin.001@gmail.com
2026-08-13T05:21:44Z
urn:sha1:9f7cd14951ed9b7e04176f68f5c454aa7018b3e3
[RISCV] Consolidate instruction behavior in RISCVInstrInfo
2026-08-12T13:35:21Z
Richard-Qin-X
richard.qin.001@gmail.com
2026-08-12T13:35:21Z
urn:sha1:f8daf08aba1f09c3024a70d3426891112d1662a2