rcc-project/backend/lib/Target/RISCV/RISCVPipeline.cpp, branch master
An optimizing compiler for C.
https://git.richardqin.org/rcc-project/atom?h=master
2026-08-28T11:44:49Z
[RISCV] Complete Zcmp frame lowering and optimization
2026-08-28T11:44:49Z
Richard-Qin-X
richard.qin.001@gmail.com
2026-08-28T11:44:49Z
urn:sha1:b91913184946e8381dc2d632ce37563913d5ce5f
[CodeGen] Add target machine registry
2026-08-28T10:51:10Z
Richard-Qin-X
richard.qin.001@gmail.com
2026-08-28T10:51:10Z
urn:sha1:f89d528efc0228c049c2867dcba886a56bac8619
[RISCV] Separate calling convention assignment
2026-08-28T06:07:11Z
Richard-Qin-X
richard.qin.001@gmail.com
2026-08-28T06:07:11Z
urn:sha1:6e8feb15a0d256ca19e88185f78c81f689ce7d34
[RISCV] Implement push-pop optimization
2026-08-26T09:56:11Z
Richard-Qin-X
richard.qin.001@gmail.com
2026-08-26T09:55:16Z
urn:sha1:7b3dcced70be227bb43e71d84d11a2f15fb25072
[CodeGen] Implement RISC-V finalize-isel
2026-08-26T09:38:21Z
Richard-Qin-X
richard.qin.001@gmail.com
2026-08-26T09:38:21Z
urn:sha1:36c4344ddf1866005c62910166ca077bf2e8f62e
[RISCV] Optimize W instructions
2026-08-25T16:34:09Z
Richard-Qin-X
richard.qin.001@gmail.com
2026-08-25T16:34:09Z
urn:sha1:73ff142aa16a29c18d09564f0b7e41940fcf786c
[CodeGen] Implement the greedy register allocator pipeline
2026-08-24T19:11:23Z
Richard-Qin-X
richard.qin.001@gmail.com
2026-08-24T19:11:23Z
urn:sha1:f5d9ddc085055d28d6f9fb3730c3566097f43fb2
[RISCV] Implement make-compressible pass
2026-08-24T18:38:56Z
Richard-Qin-X
richard.qin.001@gmail.com
2026-08-24T18:38:56Z
urn:sha1:c3932f55208e3fe2019d26a0e5af421c0b644872
[RISCV] Implement base offset merging
2026-08-24T17:50:02Z
Richard-Qin-X
richard.qin.001@gmail.com
2026-08-24T17:50:02Z
urn:sha1:6dc798fbdbef20670317742a8c1d12f47e9d1c05
[RISCV] Implement Zcmp move merging
2026-08-24T17:43:04Z
Richard-Qin-X
richard.qin.001@gmail.com
2026-08-24T17:43:04Z
urn:sha1:9e89d1d718977749ca798b27b7ad45e1781602c2