rcc-project/backend/lib/Target/RISCV/RISCVRegisterAllocation.cpp, branch master
An optimizing compiler for C.
https://git.richardqin.org/rcc-project/atom?h=master
2026-08-24T19:11:23Z
[CodeGen] Implement the greedy register allocator pipeline
2026-08-24T19:11:23Z
Richard-Qin-X
richard.qin.001@gmail.com
2026-08-24T19:11:23Z
urn:sha1:f5d9ddc085055d28d6f9fb3730c3566097f43fb2
[RISCV][GlobalISel] Generate indirect branch selection
2026-08-18T18:50:30Z
Richard-Qin-X
richard.qin.001@gmail.com
2026-08-18T18:50:30Z
urn:sha1:6c97d54954112be9a5badacaec8efa1d05bd7d15
[RISCV] Use the generated opcode conversion
2026-08-13T05:21:44Z
Richard-Qin-X
richard.qin.001@gmail.com
2026-08-13T05:21:44Z
urn:sha1:9f7cd14951ed9b7e04176f68f5c454aa7018b3e3
[RISCV] Split the GlobalISel target components
2026-08-12T14:37:49Z
Richard-Qin-X
richard.qin.001@gmail.com
2026-08-12T14:37:49Z
urn:sha1:3341938bb644e6fc39afa6a8fcb1306604999e42
[RISCV] Make target memory operands optional
2026-08-11T18:35:25Z
Richard-Qin-X
richard.qin.001@gmail.com
2026-08-11T18:35:25Z
urn:sha1:705ebca5d37ee30e9cd517fed5f09dbf12113e6b
[RISCV] Model typed floating-point register views
2026-08-11T15:44:57Z
Richard-Qin-X
richard.qin.001@gmail.com
2026-08-11T15:44:57Z
urn:sha1:e6cd1347cc2c76babe56842e1b7bd05d68fe9584
[RISCV] Match LLVM call-frame pseudo semantics
2026-08-11T12:08:36Z
Richard-Qin-X
richard.qin.001@gmail.com
2026-08-11T12:08:36Z
urn:sha1:551f0b3fcd6f797ed6dca90f39123b0359396dcb
[CodeGen] Implement RV64GC frame lowering
2026-08-09T05:23:48Z
Richard-Qin-X
richard.qin.001@gmail.com
2026-08-09T05:23:48Z
urn:sha1:da8bc76b4bf7d1a7b025d6c8ef5809551467dcc7
[CodeGen] Complete register allocation infrastructure
2026-08-08T20:40:17Z
Richard-Qin-X
richard.qin.001@gmail.com
2026-08-08T20:40:17Z
urn:sha1:e5fdceb9b869f010a2a75638fd38aaf1867f3008