rcc-project/backend/lib/Target/RISCV/RISCVTarget.cpp, branch master

rcc-project/backend/lib/Target/RISCV/RISCVTarget.cpp, branch master An optimizing compiler for C. https://git.richardqin.org/rcc-project/atom?h=master 2026-08-18T18:50:30Z [RISCV][GlobalISel] Generate indirect branch selection 2026-08-18T18:50:30Z Richard-Qin-X richard.qin.001@gmail.com 2026-08-18T18:50:30Z urn:sha1:6c97d54954112be9a5badacaec8efa1d05bd7d15 [GlobalISel] Lower stack operations 2026-08-14T20:48:16Z Richard-Qin-X richard.qin.001@gmail.com 2026-08-14T20:48:16Z urn:sha1:32a365a2dc0096b4421fb3947b32d971b7f34c40 [GlobalISel] Match LLVM legalization value tracking 2026-08-14T12:35:54Z Richard-Qin-X richard.qin.001@gmail.com 2026-08-14T12:35:54Z urn:sha1:97e5fbaa55b4672db36123c2425d05a4738452ab [RISCV] Describe vector tuple registers 2026-08-11T19:33:45Z Richard-Qin-X richard.qin.001@gmail.com 2026-08-11T19:33:45Z urn:sha1:ce691f04c3eb1a972419187884f926de9632b7cf [RISCV] Model typed floating-point register views 2026-08-11T15:44:57Z Richard-Qin-X richard.qin.001@gmail.com 2026-08-11T15:44:57Z urn:sha1:e6cd1347cc2c76babe56842e1b7bd05d68fe9584 [RISCV] Add LP64 calling-convention facts 2026-08-11T12:26:56Z Richard-Qin-X richard.qin.001@gmail.com 2026-08-11T12:26:56Z urn:sha1:38626ed37c9ea78c76c12dae4806b750881fd910 [RISCV] Legalize fixed-baseline RV64 MachineIR 2026-08-11T09:38:11Z Richard-Qin-X richard.qin.001@gmail.com 2026-08-11T09:38:11Z urn:sha1:4fe5ee649927d54d6fb74904d7b97ad0f63fd587 [RISCV] Complete RV64GC instruction description 2026-08-07T14:03:11Z Richard-Qin-X richard.qin.001@gmail.com 2026-08-07T14:03:11Z urn:sha1:3e15bfd7b075209ec3b65d30d0611e060f6fbb77 [RISCV] Add generated RV64GC register description 2026-08-06T18:15:09Z Richard-Qin-X richard.qin.001@gmail.com 2026-08-06T18:15:09Z urn:sha1:e16de95dce32f077361577377d5c52fc4ad78339 Add an RCC-owned build-time target description generator and the initial RV64GC register model. Keep ABI aliases separate from canonical MIR register spelling.