rcc-project/backend/unittests/Target/RISCVRegisterAllocationTest.cpp, branch master
An optimizing compiler for C.
https://git.richardqin.org/rcc-project/atom?h=master
2026-08-13T15:55:38Z
[CodeGen] Unify scalar low-level types
2026-08-13T15:55:38Z
Richard-Qin-X
richard.qin.001@gmail.com
2026-08-13T15:55:38Z
urn:sha1:aa69e15c6909c3b162b15f5326f0a72ba9bb7163
[RISCV] Use the generated opcode conversion
2026-08-13T05:21:44Z
Richard-Qin-X
richard.qin.001@gmail.com
2026-08-13T05:21:44Z
urn:sha1:9f7cd14951ed9b7e04176f68f5c454aa7018b3e3
[CodeGen] Align pass manager ownership
2026-08-12T21:45:37Z
Richard-Qin-X
richard.qin.001@gmail.com
2026-08-12T21:45:37Z
urn:sha1:236082a0fe4dcd0362c5c74923a93e3db6a01291
[CodeGen] Split machine liveness components
2026-08-12T20:17:52Z
Richard-Qin-X
richard.qin.001@gmail.com
2026-08-12T20:17:52Z
urn:sha1:a2f8d7c5e22b510965327383410bd576f7cf28e7
[RISCV] Split the GlobalISel target components
2026-08-12T14:37:49Z
Richard-Qin-X
richard.qin.001@gmail.com
2026-08-12T14:37:49Z
urn:sha1:3341938bb644e6fc39afa6a8fcb1306604999e42
[RISCV] Model typed floating-point register views
2026-08-11T15:44:57Z
Richard-Qin-X
richard.qin.001@gmail.com
2026-08-11T15:44:57Z
urn:sha1:e6cd1347cc2c76babe56842e1b7bd05d68fe9584
[CodeGen] Implement RV64GC frame lowering
2026-08-09T05:23:48Z
Richard-Qin-X
richard.qin.001@gmail.com
2026-08-09T05:23:48Z
urn:sha1:da8bc76b4bf7d1a7b025d6c8ef5809551467dcc7
[CodeGen] Complete register allocation infrastructure
2026-08-08T20:40:17Z
Richard-Qin-X
richard.qin.001@gmail.com
2026-08-08T20:40:17Z
urn:sha1:e5fdceb9b869f010a2a75638fd38aaf1867f3008