rcc-project/backend/unittests/Target/RISCVSSAExitTest.cpp, branch master
An optimizing compiler for C.
https://git.richardqin.org/rcc-project/atom?h=master
2026-08-13T15:55:38Z
[CodeGen] Unify scalar low-level types
2026-08-13T15:55:38Z
Richard-Qin-X
richard.qin.001@gmail.com
2026-08-13T15:55:38Z
urn:sha1:aa69e15c6909c3b162b15f5326f0a72ba9bb7163
[RISCV] Use the generated opcode conversion
2026-08-13T05:21:44Z
Richard-Qin-X
richard.qin.001@gmail.com
2026-08-13T05:21:44Z
urn:sha1:9f7cd14951ed9b7e04176f68f5c454aa7018b3e3
[CodeGen] Align pass manager ownership
2026-08-12T21:45:37Z
Richard-Qin-X
richard.qin.001@gmail.com
2026-08-12T21:45:37Z
urn:sha1:236082a0fe4dcd0362c5c74923a93e3db6a01291
[CodeGen] Split machine liveness components
2026-08-12T20:17:52Z
Richard-Qin-X
richard.qin.001@gmail.com
2026-08-12T20:17:52Z
urn:sha1:a2f8d7c5e22b510965327383410bd576f7cf28e7
[CodeGen] Split PHI elimination and two-address rewriting
2026-08-12T18:43:59Z
Richard-Qin-X
richard.qin.001@gmail.com
2026-08-12T18:43:59Z
urn:sha1:d2cd152d658955a7fb64fb9a1329bc5bee4d8317
[RISCV] Split the GlobalISel target components
2026-08-12T14:37:49Z
Richard-Qin-X
richard.qin.001@gmail.com
2026-08-12T14:37:49Z
urn:sha1:3341938bb644e6fc39afa6a8fcb1306604999e42
[RISCV] Consolidate instruction behavior in RISCVInstrInfo
2026-08-12T13:35:21Z
Richard-Qin-X
richard.qin.001@gmail.com
2026-08-12T13:35:21Z
urn:sha1:f8daf08aba1f09c3024a70d3426891112d1662a2
[CodeGen] Implement machine liveness analysis
2026-08-08T16:27:27Z
Richard-Qin-X
richard.qin.001@gmail.com
2026-08-08T16:27:27Z
urn:sha1:6c7cecc81a4c7e06e26027e21edd2cfd95a37a0b
[CodeGen] Implement machine SSA exit
2026-08-07T20:14:34Z
Richard-Qin-X
richard.qin.001@gmail.com
2026-08-07T20:14:34Z
urn:sha1:77884c967d1cbc48afcbaef7e5a35adcb3c5da1b