rcc-project/backend/unittests/Target/RISCVTargetTest.cpp, branch master An optimizing compiler for C. https://git.richardqin.org/rcc-project/atom?h=master 2026-08-11T19:33:45Z [RISCV] Describe vector tuple registers 2026-08-11T19:33:45Z Richard-Qin-X richard.qin.001@gmail.com 2026-08-11T19:33:45Z urn:sha1:ce691f04c3eb1a972419187884f926de9632b7cf [RISCV] Describe vector physical registers 2026-08-11T19:29:35Z Richard-Qin-X richard.qin.001@gmail.com 2026-08-11T19:29:35Z urn:sha1:a6f5957b69b8d492919967980d9abc6618aa5d05 [RISCV] Add Zba and Zbb instruction descriptions 2026-08-11T19:02:45Z Richard-Qin-X richard.qin.001@gmail.com 2026-08-11T19:02:45Z urn:sha1:888e9b5bb57a79f4eee88a7926cb859e04823361 [RISCV] Make call-preserved masks optional 2026-08-11T18:39:11Z Richard-Qin-X richard.qin.001@gmail.com 2026-08-11T18:39:11Z urn:sha1:46db486c089e9c2d6b05287476d7975723929acf [RISCV] Make target memory operands optional 2026-08-11T18:35:25Z Richard-Qin-X richard.qin.001@gmail.com 2026-08-11T18:35:25Z urn:sha1:705ebca5d37ee30e9cd517fed5f09dbf12113e6b [RISCV] Accept symbolic low operands in loads and stores 2026-08-11T18:01:18Z Richard-Qin-X richard.qin.001@gmail.com 2026-08-11T18:01:18Z urn:sha1:ed9afd0d9e2ecb202872b6ea4ebe5690860f9b84 [RISCV] Allow frame indices in ADDI 2026-08-11T17:36:47Z Richard-Qin-X richard.qin.001@gmail.com 2026-08-11T17:36:47Z urn:sha1:4937c5107848f1c60262ef729d466e8d90df8d47 [RISCV] Model dynamic rounding-mode state 2026-08-11T17:13:19Z Richard-Qin-X richard.qin.001@gmail.com 2026-08-11T17:13:19Z urn:sha1:2ce605211c05039131cc828bee9906996f4a1acf [RISCV] Model FFLAGS accesses 2026-08-11T17:07:48Z Richard-Qin-X richard.qin.001@gmail.com 2026-08-11T17:07:48Z urn:sha1:7819df7189a54fa5b8df657d10285f1873628d25 [RISCV] Describe the GPR select pseudo 2026-08-11T16:43:40Z Richard-Qin-X richard.qin.001@gmail.com 2026-08-11T16:43:40Z urn:sha1:128a7dbac4cdb1594b3dac9144cf044695ef2ad9