rcc-project/backend/unittests/Target/TestTarget.cpp, branch masterAn optimizing compiler for C.
https://git.richardqin.org/rcc-project/atom?h=master2026-08-06T18:15:09Z[RISCV] Add generated RV64GC register description2026-08-06T18:15:09ZRichard-Qin-Xrichard.qin.001@gmail.com2026-08-06T18:15:09Zurn:sha1:e16de95dce32f077361577377d5c52fc4ad78339
Add an RCC-owned build-time target description generator and the initial RV64GC register model. Keep ABI aliases separate from canonical MIR register spelling.
[CodeGen] Add target MIR text schema2026-08-03T11:24:30ZRichard-Qin-Xrichard.qin.001@gmail.com2026-08-03T11:24:30Zurn:sha1:432efe39315ed5ad0162f9c08dbf10941bc21dc1[CodeGen] Add target register descriptions2026-08-01T08:07:24ZRichard-Qin-Xrichard.qin.001@gmail.com2026-08-01T08:07:24Zurn:sha1:924dcd36ebed84f04729de05ec08b311a36a04c1
Introduce an immutable register topology for units, subregisters, classes, banks, and preserved masks. Bind instruction descriptors to this topology through TargetDescription so builders, cloning, and verification share one target-aware contract. Add the test-only TestTarget model and positive and negative target fact coverage.