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<title>rcc-project/backend, branch master</title>
<subtitle>An optimizing compiler for C.
</subtitle>
<id>https://git.richardqin.org/rcc-project/atom?h=master</id>
<link rel='self' href='https://git.richardqin.org/rcc-project/atom?h=master'/>
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<updated>2026-08-28T16:44:44Z</updated>
<entry>
<title>[MIR] Merge identical scalar type branches</title>
<updated>2026-08-28T16:44:44Z</updated>
<author>
<name>Richard-Qin-X</name>
<email>richard.qin.001@gmail.com</email>
</author>
<published>2026-08-28T16:44:44Z</published>
<link rel='alternate' type='text/html' href='https://git.richardqin.org/rcc-project/commit/?id=00559425828f56e26d80f5142db1052b9db4ca80'/>
<id>urn:sha1:00559425828f56e26d80f5142db1052b9db4ca80</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[RISCV] Merge identical selector cases</title>
<updated>2026-08-28T16:41:28Z</updated>
<author>
<name>Richard-Qin-X</name>
<email>richard.qin.001@gmail.com</email>
</author>
<published>2026-08-28T16:41:28Z</published>
<link rel='alternate' type='text/html' href='https://git.richardqin.org/rcc-project/commit/?id=1481dd5b62a8a914e593206d72e1aff99ced2af4'/>
<id>urn:sha1:1481dd5b62a8a914e593206d72e1aff99ced2af4</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[RISCV] Widen jump table entry size arithmetic</title>
<updated>2026-08-28T16:38:11Z</updated>
<author>
<name>Richard-Qin-X</name>
<email>richard.qin.001@gmail.com</email>
</author>
<published>2026-08-28T16:38:11Z</published>
<link rel='alternate' type='text/html' href='https://git.richardqin.org/rcc-project/commit/?id=6b07676fa9177bbf971afaf898dd9997e0664b95'/>
<id>urn:sha1:6b07676fa9177bbf971afaf898dd9997e0664b95</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[RISCV] Reuse validated Zcmp frame offsets</title>
<updated>2026-08-28T16:36:55Z</updated>
<author>
<name>Richard-Qin-X</name>
<email>richard.qin.001@gmail.com</email>
</author>
<published>2026-08-28T16:36:55Z</published>
<link rel='alternate' type='text/html' href='https://git.richardqin.org/rcc-project/commit/?id=96cc3e77afff5627cf1cacf42f788a752de00f74'/>
<id>urn:sha1:96cc3e77afff5627cf1cacf42f788a752de00f74</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[RISCV] Assert merged memory offset invariants</title>
<updated>2026-08-28T16:34:24Z</updated>
<author>
<name>Richard-Qin-X</name>
<email>richard.qin.001@gmail.com</email>
</author>
<published>2026-08-28T16:34:24Z</published>
<link rel='alternate' type='text/html' href='https://git.richardqin.org/rcc-project/commit/?id=3d4bd273c2d7df2d96d2e741227e3f23b8734879'/>
<id>urn:sha1:3d4bd273c2d7df2d96d2e741227e3f23b8734879</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[RISCV] Reuse validated move registers</title>
<updated>2026-08-28T16:32:26Z</updated>
<author>
<name>Richard-Qin-X</name>
<email>richard.qin.001@gmail.com</email>
</author>
<published>2026-08-28T16:32:26Z</published>
<link rel='alternate' type='text/html' href='https://git.richardqin.org/rcc-project/commit/?id=a2b81e7789e7c24cf802f104bf851c4cbc91c3a2'/>
<id>urn:sha1:a2b81e7789e7c24cf802f104bf851c4cbc91c3a2</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[GlobalISel] Bind register bank optionals once</title>
<updated>2026-08-28T16:30:28Z</updated>
<author>
<name>Richard-Qin-X</name>
<email>richard.qin.001@gmail.com</email>
</author>
<published>2026-08-28T16:30:28Z</published>
<link rel='alternate' type='text/html' href='https://git.richardqin.org/rcc-project/commit/?id=27f840d377d8288deb3ecf936cb70e246d7da162'/>
<id>urn:sha1:27f840d377d8288deb3ecf936cb70e246d7da162</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[GlobalISel] Assert vector element type invariants</title>
<updated>2026-08-28T16:28:29Z</updated>
<author>
<name>Richard-Qin-X</name>
<email>richard.qin.001@gmail.com</email>
</author>
<published>2026-08-28T16:28:29Z</published>
<link rel='alternate' type='text/html' href='https://git.richardqin.org/rcc-project/commit/?id=14a02f58dffc0e34f2cea914f207d9d37773b759'/>
<id>urn:sha1:14a02f58dffc0e34f2cea914f207d9d37773b759</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[CodeGen] Bind virtual register types once</title>
<updated>2026-08-28T16:25:20Z</updated>
<author>
<name>Richard-Qin-X</name>
<email>richard.qin.001@gmail.com</email>
</author>
<published>2026-08-28T16:25:20Z</published>
<link rel='alternate' type='text/html' href='https://git.richardqin.org/rcc-project/commit/?id=294cefacabb7dbf954cbb70dbb724745eeba3abc'/>
<id>urn:sha1:294cefacabb7dbf954cbb70dbb724745eeba3abc</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[CodeGen] Apply LLVM declaration style</title>
<updated>2026-08-28T16:24:17Z</updated>
<author>
<name>Richard-Qin-X</name>
<email>richard.qin.001@gmail.com</email>
</author>
<published>2026-08-28T16:24:17Z</published>
<link rel='alternate' type='text/html' href='https://git.richardqin.org/rcc-project/commit/?id=36b5b862c8ab2f75606e23466a3c758ff6d9358b'/>
<id>urn:sha1:36b5b862c8ab2f75606e23466a3c758ff6d9358b</id>
<content type='text'>
</content>
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