rcc-project/rv64cpu/rtl/core, branch masterA collection of systems software, from virtual machines and compilers to developer tools and terminal applications.
https://git.richardqin.org/rcc-project/atom?h=master2026-11-06T19:16:17Zrefactor: align RTL module names with files2026-11-06T19:16:17ZRichard Qinrichard.qin.x@gmail.com2026-11-06T19:16:17Zurn:sha1:e0948e3fc10029ba4bb4d48d7b5daae94fe575b9refactor: rename RTL source files2026-11-06T19:14:46ZRichard Qinrichard.qin.x@gmail.com2026-11-06T19:14:46Zurn:sha1:6f57dd79572c177b775a934bee54ceb85a55c28arefactor: reorganize RTL directory structure2026-11-06T19:10:08ZRichard Qinrichard.qin.x@gmail.com2026-11-06T19:10:08Zurn:sha1:1410d3309ae9557ab102942bbc4d8449f2206fe5checkpoint: preserve current RV64 CPU development state2026-11-06T18:59:33ZRichard Qinrichard.qin.x@gmail.com2026-11-06T18:59:33Zurn:sha1:bc3ec25107314be3cd816c0b669d82338e892806refactor: standardize interrupt signal naming across the codebase2026-04-07T15:31:27ZRichard Qinrichard.qin.x@gmail.com2026-04-07T15:31:27Zurn:sha1:c67ba709482821f37d63601b001ac07e6db867b6refactor: standardize interrupt signal naming across the codebase2026-04-07T14:42:49ZRichard Qinrichard.qin.x@gmail.com2026-04-07T14:42:49Zurn:sha1:639212a826659c591db3202607c4a47e1049b92afeat(tlb): enhance TLB functionality with ASID-targeted flush and additional test cases2026-04-07T13:21:03ZRichard Qinrichard.qin.x@gmail.com2026-04-07T13:21:03Zurn:sha1:328d4ef7537a98bab8f6891a0280cda9e03b0ceefeat(tlb): add parameterized L1 TLB module and corresponding unit tests2026-04-01T07:32:40ZRichard Qinrichard.qin.x@gmail.com2026-04-01T07:32:40Zurn:sha1:9c34902e4a763109d7d6251781bcb92f6bc68c56feat: Complete CSR/privileged/exception interrupt path and fill in strict acceptance tests2026-03-31T16:58:22ZRichard Qinrichard.qin.x@gmail.com2026-03-31T16:58:22Zurn:sha1:cf0476e565c74082f011a6c428095e60a743b822
- Refactor trap/CSR data path in the Core, unified with trap_ctrl interface to drive CSR update and return process
- Improve critical paths for exception/interrupt handling: ecall, illegal, load fault, external interrupt, mret/sret return
- Adjust pipeline stage registers with flush/stall coordination, fix residual control signal issues in trap scenarios
- Enhance decode and related pipeline module behavior consistency, fill in missing control signal propagation across registers
- Expand core integration testing, add trap/interrupt scenarios and CLI dispatch that can be executed per case
- Extend CSR unit test coverage: read/write semantics, privilege switching, delegation and nested returns, illegal access protection, etc.
- Register new core scenario cases in CTest to form a regression-capable P2 strict acceptance suite
Verification:
- Build passed
- Full CTest passed (22/22)
Trap Control unit and tests2026-03-18T19:16:03ZRichard Qinrichard.qin.x@gmail.com2026-03-18T19:16:03Zurn:sha1:ab6a21ae1099bff120111b8a9dcfa50c9fcad5a1