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-rw-r--r--rv64cpu/rtl/core/regfile.sv60
-rw-r--r--rv64cpu/tb/CMakeLists.txt26
-rw-r--r--rv64cpu/tb/unit/tb_regfile.cc99
3 files changed, 172 insertions, 13 deletions
diff --git a/rv64cpu/rtl/core/regfile.sv b/rv64cpu/rtl/core/regfile.sv
new file mode 100644
index 0000000..83e09b7
--- /dev/null
+++ b/rv64cpu/rtl/core/regfile.sv
@@ -0,0 +1,60 @@
+// Richard CPU
+// Copyright (C) 2026 Richard Qin
+
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+
+// You should have received a copy of the GNU General Public License
+// along with this program. If not, see <https://www.gnu.org/licenses/>.
+
+// File path: rtl/core/regfile.sv
+// Description: 64-bit Register File
+
+module regfile
+ import rv64_pkg::*;
+(
+ input logic clk, // Clock signal
+ input logic rst, // Reset signal active high
+
+ // Read port 1
+ input logic [4:0] rs1_addr, // Read address 1
+ output logic [XLEN-1:0] rs1_val, // Read data 1
+
+ // Read port 2
+ input logic [4:0] rs2_addr, // Read address 2
+ output logic [XLEN-1:0] rs2_val, // Read data 2
+
+ // Write port
+ input logic [4:0] rd_addr, // Write address
+ input logic [XLEN-1:0] rd_val, // Write data
+ input logic we // Write enable signal
+);
+
+ // Register file storage
+ logic [XLEN-1:0] regs [0:31];
+
+ // Read Logic (combinational logic)
+ assign rs1_val = (rs1_addr == 5'b0) ? '0 : regs[rs1_addr];
+ assign rs2_val = (rs2_addr == 5'b0) ? '0 : regs[rs2_addr];
+
+ // Write Logic (sequential logic)
+ always_ff @(posedge clk) begin
+ if (rst) begin
+ for (int i = 0; i < 32; i++) begin
+ regs[i] <= '0;
+ end
+ end else begin
+ if (we && rd_addr != 5'b0) begin
+ regs[rd_addr] <= rd_val;
+ end
+ end
+ end
+
+endmodule
diff --git a/rv64cpu/tb/CMakeLists.txt b/rv64cpu/tb/CMakeLists.txt
index 73df088..0643120 100644
--- a/rv64cpu/tb/CMakeLists.txt
+++ b/rv64cpu/tb/CMakeLists.txt
@@ -45,17 +45,17 @@ add_verilator_target(
# SOURCES ${RTL_CORE_DIR}/include/rv64_pkg.sv
# ${RTL_CORE_DIR}/decoder.sv
# INCLUDE_DIRS ${RTL_COMMON_INCLUDES}
-# TB_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/unit/tb_decoder.cpp
-# )
-#
-# add_verilator_target(
-# NAME tb_regfile
-# TOP_MODULE regfile
-# SOURCES ${RTL_CORE_DIR}/include/rv64_pkg.sv
-# ${RTL_CORE_DIR}/regfile.sv
-# INCLUDE_DIRS ${RTL_COMMON_INCLUDES}
-# TB_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/unit/tb_regfile.cpp
+# TB_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/unit/tb_decoder.cc
# )
+
+add_verilator_target(
+ NAME tb_regfile
+ TOP_MODULE regfile
+ SOURCES ${RTL_CORE_DIR}/include/rv64_pkg.sv
+ ${RTL_CORE_DIR}/regfile.sv
+ INCLUDE_DIRS ${RTL_COMMON_INCLUDES}
+ TB_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/unit/tb_regfile.cc
+)
#
# add_verilator_target(
# NAME tb_csr
@@ -64,7 +64,7 @@ add_verilator_target(
# ${RTL_CORE_DIR}/include/csr_pkg.sv
# ${RTL_CORE_DIR}/csr_unit.sv
# INCLUDE_DIRS ${RTL_COMMON_INCLUDES}
-# TB_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/unit/tb_csr.cpp
+# TB_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/unit/tb_csr.cc
# )
# ═══════════════════════════════════════════════════════════════════════════════════
@@ -76,7 +76,7 @@ add_verilator_target(
# TOP_MODULE richard_core
# SOURCES ${ALL_RTL_SOURCES}
# INCLUDE_DIRS ${RTL_COMMON_INCLUDES}
-# TB_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/core/tb_core.cpp
+# TB_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/core/tb_core.cc
# )
# ═══════════════════════════════════════════════════════════════════════════════════
@@ -88,7 +88,7 @@ add_verilator_target(
# TOP_MODULE richard_soc
# SOURCES ${ALL_RTL_SOURCES}
# INCLUDE_DIRS ${RTL_COMMON_INCLUDES}
-# TB_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/soc/tb_soc.cpp
+# TB_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/soc/tb_soc.cc
# EXTRA_FLAGS --threads 2
# )
diff --git a/rv64cpu/tb/unit/tb_regfile.cc b/rv64cpu/tb/unit/tb_regfile.cc
new file mode 100644
index 0000000..c96e395
--- /dev/null
+++ b/rv64cpu/tb/unit/tb_regfile.cc
@@ -0,0 +1,99 @@
+// Richard CPU
+// Copyright (C) 2026 Richard Qin
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+
+// You should have received a copy of the GNU General Public License
+// along with this program. If not, see <https://www.gnu.org/licenses/>.
+
+// File path: tb/unit/tb_regfile.cc
+// Description: Register file unit test
+
+#include <iostream>
+#include <cassert>
+#include <verilated.h>
+#include "Vregfile.h"
+
+void tick(Vregfile* dut) {
+ dut->clk = 0;
+ dut->eval();
+ dut->clk = 1;
+ dut->eval();
+ dut->clk = 0;
+ dut->eval();
+}
+
+int main(int argc, char** argv) {
+ Verilated::commandArgs(argc, argv);
+ Vregfile* dut = new Vregfile;
+
+ dut->clk = 0;
+ dut->rst = 0;
+ dut->we = 0;
+ dut->rd_addr = 0;
+ dut->rd_val = 0;
+ dut->rs1_addr = 0;
+ dut->rs2_addr = 0;
+
+ std::cout << "Starting register file unit test" << std::endl;
+
+ // Test 1: Reset
+ dut->rst = 1;
+ tick(dut);
+ dut->rst = 0;
+ std::cout << "[PASS] Reset complete" << std::endl;
+
+ // Test 2: Write and read
+ dut->we = 1;
+ dut->rd_addr = 5;
+ dut->rd_val = 0xDEADBEEF;
+ tick(dut);
+
+ dut->we = 0;
+ dut->rs1_addr = 5;
+ dut->eval();
+ assert(dut->rs1_val == 0xDEADBEEF);
+ std::cout << "[PASS] Write and read (x5) complete" << std::endl;
+
+ // Test 3: x0
+ dut->we = 1;
+ dut->rd_addr = 0;
+ dut->rd_val = 0x12345678;
+ tick(dut);
+
+ dut->we = 0;
+ dut->rs2_addr = 0;
+ dut->eval();
+ assert(dut->rs2_val == 0);
+ std::cout << "[PASS] Write and read (x0) complete" << std::endl;
+
+ // Test 4: Dual-port simultaneous read
+ dut->we = 1;
+ dut->rd_addr = 6;
+ dut->rd_val = 0x87654321;
+ tick(dut);
+
+ dut->we = 1;
+ dut->rd_addr = 7;
+ dut->rd_val = 0x11223344;
+ tick(dut);
+
+ dut->rs1_addr = 6;
+ dut->rs2_addr = 7;
+ dut->eval();
+
+ assert(dut->rs1_val == 0x87654321 && dut->rs2_val == 0x11223344);
+ std::cout << "[PASS] Dual-port simultaneous read complete" << std::endl;
+
+ std::cout << "Register file unit test complete" << std::endl;
+
+ delete dut;
+ exit(0);
+} \ No newline at end of file
generated by cgit v1.2.3 (git 2.46.0) at 2026-11-09 05:27:09 +0000