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* [CodeGen] Treat reserved registers as always liveRichard-Qin-X2026-08-112-0/+52
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* [CodeGen] Accept conservative physical live-insRichard-Qin-X2026-08-112-2/+8
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* [RISCV] Model typed floating-point register viewsRichard-Qin-X2026-08-1114-155/+303
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* [RISCV] Order call operands like LLVM MIRRichard-Qin-X2026-08-112-15/+28
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* [RISCV] Add LP64 calling-convention factsRichard-Qin-X2026-08-119-69/+146
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* [CodeGen] Remove redundant numeric call-site IDsRichard-Qin-X2026-08-1110-46/+18
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* [RISCV] Derive the generated instruction count in testsRichard-Qin-X2026-08-111-1/+5
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* [RISCV] Match LLVM call-frame pseudo semanticsRichard-Qin-X2026-08-116-85/+80
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* [RISCV] Use canonical copies for full ABI valuesRichard-Qin-X2026-08-112-7/+15
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* [RISCV] Lower multiply without M through libcallsRichard-Qin-X2026-08-112-3/+182
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* [RISCV] Accept generic scalars in call loweringRichard-Qin-X2026-08-112-3/+18
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* [RISCV] Honor invocation subtarget featuresRichard-Qin-X2026-08-1110-18/+230
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* [RISCV] Fold narrow binary artifact chainsRichard-Qin-X2026-08-112-15/+118
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* [CodeGen] Revisit instructions invalidated by legalizationRichard-Qin-X2026-08-112-12/+72
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* [RISCV] Preserve folded constant placementRichard-Qin-X2026-08-112-3/+38
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* [RISCV] Reuse compare operand extensionsRichard-Qin-X2026-08-112-0/+71
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* [RISCV] Legalize integer compares to RV64 containersRichard-Qin-X2026-08-112-20/+204
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* [RISCV] Preserve live constants when folding extensionsRichard-Qin-X2026-08-112-2/+52
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* [MIR] Omit absent zero-offset MMO basesRichard-Qin-X2026-08-112-5/+14
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* [RISCV] Lower cmpxchg with successRichard-Qin-X2026-08-112-1/+131
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* [RISCV] Preserve narrow cmpxchg results when wideningRichard-Qin-X2026-08-112-2/+40
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* [RISCV] Legalize narrow atomic compare exchangeRichard-Qin-X2026-08-113-2/+228
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* [MIR] Parse one-ordering compare-exchange MMOsRichard-Qin-X2026-08-114-52/+94
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* [RISCV] Legalize fixed-baseline RV64 MachineIRRichard-Qin-X2026-08-1118-65/+3013
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* [MIR] Accept fixed-baseline LLVM syntaxRichard-Qin-X2026-08-1153-650/+2429
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* [Tooling] Complete backend tooling and validationRichard-Qin-X2026-08-1090-2995/+11345
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* [MC] Implement RV64GC object emissionRichard-Qin-X2026-08-0952-58/+7361
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* [MC] Implement RV64GC assembly emissionRichard-Qin-X2026-08-0952-3/+5886
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* [CodeGen] Implement machine optimization and schedulingRichard-Qin-X2026-08-0991-40/+14212
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* [CodeGen] Implement RV64GC frame loweringRichard-Qin-X2026-08-0929-9/+4264
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* [CodeGen] Complete register allocation infrastructureRichard-Qin-X2026-08-0970-194/+7008
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* [CodeGen] Implement machine liveness analysisRichard-Qin-X2026-08-0915-53/+3294
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* [CodeGen] Implement machine SSA exitRichard-Qin-X2026-08-0822-56/+3594
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* [CodeGen] Implement RV64GC legalization and instruction selectionRichard-Qin-X2026-08-0811-0/+5793
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* [CodeGen] Complete machine pass and ABI lowering infrastructureRichard-Qin-X2026-08-0725-0/+10628
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* [RISCV] Complete RV64GC instruction descriptionRichard-Qin-X2026-08-0711-87/+5460
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* [RISCV] Add generated RV64GC register descriptionRichard-Qin-X2026-08-0719-9/+2062
| | | | Add an RCC-owned build-time target description generator and the initial RV64GC register model. Keep ABI aliases separate from canonical MIR register spelling.
* [MIR] Complete document parsing and printingRichard-Qin-X2026-08-0745-218/+11465
| | | | Implement the single LLVM-compatible MIR document path with structured\nembedded-IR references, YAML mappings, constants, and deterministic printing.\n\nKeep pointer LLT widths DataLayout-derived, reject layout-dependent output\nwhen embedded IR is omitted, and record the fixed-baseline compatibility\ncontract and regression coverage.
* [MIR] Add machine instruction parser and printerRichard-Qin-X2026-08-0415-19/+5394
| | | | Parse MachineFunction bodies in two passes and serialize the same MachineIR model in complete or readable form. Extend instruction attachments and memory operands required by the fixed LLVM MIR grammar, and cover deterministic parse-print round trips.
* [MIR] Add machine instruction lexerRichard-Qin-X2026-08-035-4/+1569
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* [CodeGen] Add target MIR text schemaRichard-Qin-X2026-08-0320-50/+1363
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* [CodeGen] Model complete MIR operandsRichard-Qin-X2026-08-0315-5/+1572
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* [CodeGen] Model machine debug metadataRichard-Qin-X2026-08-0222-38/+814
| | | | Replace marker-based metadata operands with scoped references and inline DIExpression values. Add structured DILocation chains, instruction debug attachments, stack variable records, and entry values with unified verification, builder support, and deterministic cloning.
* [CodeGen] Add machine metadata graphsRichard-Qin-X2026-08-028-0/+492
| | | | Model ordered function-local metadata tuples with explicit embedded-IR and MachineFunction reference scopes. Preserve slot zero, distinct nodes, forward references, and cyclic graphs while verifying function-local closure and cloning the graph deterministically.
* [CodeGen] Track debug instruction identitiesRichard-Qin-X2026-08-0110-0/+471
| | | | Add monotonic MIR debug instruction numbers and structured value substitutions. Verify live number uniqueness, meta-instruction exclusion, substitution graph integrity, and target subregister references while preserving debug identities during cloning.
* [CodeGen] Add machine function recordsRichard-Qin-X2026-08-018-0/+724
| | | | Represent callee-saved registers, call-site information, called globals, and prefetch targets in the core MachineIR model. Verify target and instruction references and remap StableIDs during explicit function cloning.
* [CodeGen] Add MIR function and block attributesRichard-Qin-X2026-08-0115-26/+745
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* [MIR] Add compilation unit reference contextRichard-Qin-X2026-08-0112-0/+1251
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* [Support] Add MIR YAML parsing infrastructureRichard-Qin-X2026-08-018-5/+1890
| | | | Introduce source ranges, deterministic text diagnostics, and an independently authored YAML stream parser for the fixed LLVM MIR container shapes. Record the compatibility matrix and Stage 6 validation state.
* [CodeGen] Add target register descriptionsRichard-Qin-X2026-08-0124-156/+2821
| | | | Introduce an immutable register topology for units, subregisters, classes, banks, and preserved masks. Bind instruction descriptors to this topology through TargetDescription so builders, cloning, and verification share one target-aware contract. Add the test-only TestTarget model and positive and negative target fact coverage.
generated by cgit v1.2.3 (git 2.46.0) at 2026-10-29 12:10:16 +0000