aboutsummaryrefslogtreecommitdiff
Commit message (Collapse)AuthorAgeFilesLines
* [CodeGen] Run SSA exit transformations onceRichard-Qin-X2026-08-264-57/+22
|
* [GlobalISel] Run machine transformations onceRichard-Qin-X2026-08-266-78/+20
|
* [CodeGen] Centralize machine pass property validationRichard-Qin-X2026-08-2624-169/+0
|
* [RISCV] Implement push-pop optimizationRichard-Qin-X2026-08-2610-27/+318
|
* [CodeGen] Implement RISC-V finalize-iselRichard-Qin-X2026-08-2610-5/+667
|
* [CodeGen] Implement reaching-def analysis printingRichard-Qin-X2026-08-2610-43/+554
|
* [RISCV] Optimize W instructionsRichard-Qin-X2026-08-264-0/+642
|
* [CodeGen] Implement the greedy register allocator pipelineRichard-Qin-X2026-08-2516-46/+454
|
* [RISCV] Implement make-compressible passRichard-Qin-X2026-08-2511-4/+492
|
* [CodeGen] Implement RISC-V machine outliningRichard-Qin-X2026-08-2510-6/+1167
|
* [RISCV] Implement base offset mergingRichard-Qin-X2026-08-254-0/+522
|
* [RISCV] Implement Zcmp move mergingRichard-Qin-X2026-08-259-0/+392
|
* [CodeGen] Implement CFI instruction insertionRichard-Qin-X2026-08-246-1/+478
|
* [RISCV] Implement save and restore libcallsRichard-Qin-X2026-08-243-75/+347
|
* [CodeGen] Match LLVM callee-save live-insRichard-Qin-X2026-08-241-1/+1
|
* [RISCV] Match LLVM compressed stack frame loweringRichard-Qin-X2026-08-247-104/+102
|
* [RISCV] Match LLVM large call frame loweringRichard-Qin-X2026-08-243-209/+290
|
* [RISCV] Match LLVM emergency spill layoutRichard-Qin-X2026-08-2415-230/+393
|
* [CodeGen] Match LLVM machine combiner semanticsRichard-Qin-X2026-08-246-343/+179
|
* [RISCV] Match LLVM frame lowering semanticsRichard-Qin-X2026-08-2413-155/+164
|
* [CodeGen] Implement RISC-V peephole branch optimizationRichard-Qin-X2026-08-246-1/+359
|
* [RISCV] Generate MC pseudo loweringRichard-Qin-X2026-08-2215-207/+392
|
* [CodeGen] Match LLVM machine debug strippingRichard-Qin-X2026-08-229-2/+85
|
* [CodeGen] Generate RISC-V macro fusion rulesRichard-Qin-X2026-08-2237-91/+1323
|
* [CodeGen] Match LLVM final verifier contractRichard-Qin-X2026-08-191-2/+2
|
* [CodeGen] Match LLVM finalization contractRichard-Qin-X2026-08-191-2/+2
|
* [CodeGen] Match LLVM late pseudo contractRichard-Qin-X2026-08-191-2/+2
|
* [CodeGen] Remove RCC fallthrough normalizationRichard-Qin-X2026-08-195-270/+0
|
* [CodeGen] Match LLVM block placement contractRichard-Qin-X2026-08-191-6/+2
|
* [CodeGen] Unify LLVM branch folding pipelineRichard-Qin-X2026-08-197-469/+310
|
* [CodeGen] Match LLVM tail duplication contractRichard-Qin-X2026-08-191-9/+1
|
* [CodeGen] Match LLVM post-machine scheduler contractRichard-Qin-X2026-08-191-7/+1
|
* [CodeGen] Match LLVM post-RA pseudo expansion contractRichard-Qin-X2026-08-191-7/+1
|
* [CodeGen] Remove non-LLVM machine DCE placementsRichard-Qin-X2026-08-192-8/+2
|
* [CodeGen] Remove unsupported post-frame combinerRichard-Qin-X2026-08-194-25/+1
|
* [CodeGen] Remove unsupported pre-PEI pseudo expansionRichard-Qin-X2026-08-196-57/+3
|
* [CodeGen] Match LLVM shrink wrapping contractRichard-Qin-X2026-08-191-7/+1
|
* [CodeGen] Match LLVM post-RA sink contractRichard-Qin-X2026-08-191-3/+1
|
* [CodeGen] Match LLVM post-RA LICM contractRichard-Qin-X2026-08-191-3/+1
|
* [CodeGen] Match LLVM post-RA combiner contractRichard-Qin-X2026-08-191-1/+1
|
* [CodeGen] Match LLVM stack slot coloring contractRichard-Qin-X2026-08-191-6/+1
|
* [CodeGen] Match LLVM PBQP allocator input contractRichard-Qin-X2026-08-191-4/+2
|
* [CodeGen] Match LLVM machine scheduler contractRichard-Qin-X2026-08-191-6/+1
|
* [CodeGen] Match LLVM machine sink input contractRichard-Qin-X2026-08-191-2/+2
|
* [CodeGen] Match LLVM prologepilog input contractRichard-Qin-X2026-08-191-2/+1
|
* [GlobalISel] Generate prelegalizer combiner rulesRichard-Qin-X2026-08-1919-16/+1381
|
* [RISCV][GlobalISel] Select and expand global addressesRichard-Qin-X2026-08-1931-19/+495
|
* [RISCV][GlobalISel] Generate integer store selectionRichard-Qin-X2026-08-192-80/+76
|
* [RISCV][GlobalISel] Generate integer load selectionRichard-Qin-X2026-08-199-80/+346
|
* [RISCV][GlobalISel] Generate frame index selectionRichard-Qin-X2026-08-192-0/+17
|
generated by cgit v1.2.3 (git 2.46.0) at 2026-10-29 22:01:52 +0000