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* [MC] Implement RV64GC assembly emissionRichard-Qin-X2026-08-0952-3/+5886
* [CodeGen] Implement machine optimization and schedulingRichard-Qin-X2026-08-0991-40/+14212
* [CodeGen] Implement RV64GC frame loweringRichard-Qin-X2026-08-0929-9/+4264
* [CodeGen] Complete register allocation infrastructureRichard-Qin-X2026-08-0970-194/+7008
* [CodeGen] Implement machine liveness analysisRichard-Qin-X2026-08-0915-53/+3294
* [CodeGen] Implement machine SSA exitRichard-Qin-X2026-08-0822-56/+3594
* [CodeGen] Implement RV64GC legalization and instruction selectionRichard-Qin-X2026-08-0811-0/+5793
* [CodeGen] Complete machine pass and ABI lowering infrastructureRichard-Qin-X2026-08-0725-0/+10628
* [RISCV] Complete RV64GC instruction descriptionRichard-Qin-X2026-08-0711-87/+5460
* [RISCV] Add generated RV64GC register descriptionRichard-Qin-X2026-08-0719-9/+2062
* [MIR] Complete document parsing and printingRichard-Qin-X2026-08-0745-218/+11465
* [MIR] Add machine instruction parser and printerRichard-Qin-X2026-08-0415-19/+5394
* [MIR] Add machine instruction lexerRichard-Qin-X2026-08-035-4/+1569
* [CodeGen] Add target MIR text schemaRichard-Qin-X2026-08-0320-50/+1363
* [CodeGen] Model complete MIR operandsRichard-Qin-X2026-08-0315-5/+1572
* [CodeGen] Model machine debug metadataRichard-Qin-X2026-08-0222-38/+814
* [CodeGen] Add machine metadata graphsRichard-Qin-X2026-08-028-0/+492
* [CodeGen] Track debug instruction identitiesRichard-Qin-X2026-08-0110-0/+471
* [CodeGen] Add machine function recordsRichard-Qin-X2026-08-018-0/+724
* [CodeGen] Add MIR function and block attributesRichard-Qin-X2026-08-0115-26/+745
* [MIR] Add compilation unit reference contextRichard-Qin-X2026-08-0112-0/+1251
* [Support] Add MIR YAML parsing infrastructureRichard-Qin-X2026-08-018-5/+1890
* [CodeGen] Add target register descriptionsRichard-Qin-X2026-08-0124-156/+2821
* [CodeGen] Add target state and compilation statusRichard-Qin-X2026-08-0115-0/+1470
* [CodeGen] Add constant and jump table stateRichard-Qin-X2026-08-0121-42/+2427
* [CodeGen] Add MachineFrameInfoRichard-Qin-X2026-08-0113-20/+876
* [CodeGen] Add explicit MachineFunction cloningRichard-Qin-X2026-08-015-0/+885
* [CodeGen] Add strict MachineIR verificationRichard-Qin-X2026-08-017-0/+1044
* [CodeGen] Add transactional MachineIR builderRichard-Qin-X2026-08-019-72/+1368
* [CMake] Match LLVM EH and RTTI defaultsRichard-Qin-X2026-08-013-10/+25
* [CodeGen] Add machine instruction descriptorsRichard-Qin-X2026-08-017-0/+1186
* [CodeGen] Build the core MachineIR object modelRichard-Qin-X2026-08-0116-0/+2935
* [CodeGen] Add machine IR value semanticsRichard-Qin-X2026-08-019-5/+1071
* [CodeGen] Add core machine type primitivesRichard-Qin-X2026-08-0112-0/+1273
* [Backend] Establish standalone build infrastructureRichard-Qin-X2026-08-0120-22/+650
* [legacy] Add functional and performance test suitesRichard-Qin-X2026-06-081837-0/+463184
* [legacy] Add compiler driverRichard-Qin-X2026-06-081-0/+386
* [legacy/backend] Add RISC-V 64 instruction selection, regalloc, and emissionRichard-Qin-X2026-06-089-0/+4209
* [legacy/mid] Add target-independent ABI loweringRichard-Qin-X2026-06-081-0/+45
* [legacy/mid] Add interprocedural passes: inlining and tail-recursion eliminationRichard-Qin-X2026-06-082-0/+698
* [legacy/mid] Add control-flow optimization: if-conversionRichard-Qin-X2026-06-081-0/+127
* [legacy/mid] Add loop idiom recognition: memset/memcpy, scalar replacement, r...Richard-Qin-X2026-06-083-0/+1457
* [legacy/mid] Add loop restructuring: unrolling, unswitching, interchange, dea...Richard-Qin-X2026-06-084-0/+1990
* [legacy/mid] Add loop-invariant and induction-variable optimization: LICM, LSRRichard-Qin-X2026-06-082-0/+1214
* [legacy/mid] Add strength reduction for constant div and mulRichard-Qin-X2026-06-082-0/+397
* [legacy/mid] Add scalar optimizations: fold, copy, GVN, GCM, SCCP, reassociat...Richard-Qin-X2026-06-087-0/+2604
* [legacy/mid] Add memory SSA: construction, promotion, load/store optimizationRichard-Qin-X2026-06-084-0/+1952
* [legacy/mid] Add analysis passes: CFG, dominance, liveness, loops, aliasRichard-Qin-X2026-06-084-0/+1451
* [legacy/ir] Add SSA IR generationRichard-Qin-X2026-06-084-0/+1688
* [legacy/frontend] Add lexer, parser, and ASTRichard-Qin-X2026-06-083-0/+995
generated by cgit v1.2.3 (git 2.46.0) at 2026-10-29 11:48:53 +0000